Invention Grant
- Patent Title: Range and process compensation for a digital phase locked loop (PLL) or frequency locked loop (FLL) circuit
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Application No.: US15251570Application Date: 2016-08-30
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Publication No.: US09793906B1Publication Date: 2017-10-17
- Inventor: Gagan Midha
- Applicant: STMicroelectronics International N.V.
- Applicant Address: NL Schiphol
- Assignee: STMicroelectronics International N.V.
- Current Assignee: STMicroelectronics International N.V.
- Current Assignee Address: NL Schiphol
- Agency: Gardere Wynne Sewell LLP
- Main IPC: H03L7/06
- IPC: H03L7/06 ; H03L7/10 ; H03L7/183 ; H03L7/083 ; H03L7/091 ; H03L7/099
Abstract:
A locked loop circuit includes a controlled oscillator generate an output signal having a frequency set by an analog control signal. The analog control signal is generated by a first digital-to-analog converter (DAC) in response to a digital control signal and a bias compensation current signal. The bias compensation current signal is generated by a second DAC in response to a compensation control signal and a bias reference current. A compensation circuit adjusts the compensation control signal during compensation mode in response to a comparison of a frequency of the output signal to a frequency of a reference signal so as to drive the frequency of the output signal toward matching a desired frequency. The bias compensation current signal associated with the frequency match condition during compensation mode is then used during locked loop mode.
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