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公开(公告)号：US10027333B2
公开(公告)日：2018-07-17
申请号：US15356335
申请日：2016-11-18
Applicant: STMicroelectronics International N.V.
Inventor： Abhirup Lahiri , Nitin Gupta , Gagan Midha
Abstract: An embodiment circuit includes a first charge pump configured to generate a first current at a first node, and a second charge pump configured to generate a second current at a second node. The circuit further includes an isolation buffer coupled between the first node and the second node and an adder having a first input coupled to the second node. The circuit additionally includes an auxiliary charge pump configured to generate a third current at a second input of the adder, and an oscillator having an input coupled to an output of the adder.
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公开(公告)号：US20180062661A1
公开(公告)日：2018-03-01
申请号：US15251065
申请日：2016-08-30
Applicant: STMicroelectronics International N.V.
Inventor： Anand Kumar , Gagan Midha
CPC classification number: H03L7/093 , H03C3/095 , H03L7/0891 , H03L7/099 , H03L7/1976 , H04B1/69
Abstract: A phase or frequency locked-loop circuit includes an oscillator configured to generate an output clock signal having a frequency set by an oscillator control signal. A modulator circuit receives a first signal and a second signal and is configured to generate a control signal having a value modulated in response to the first and second signals. A filter circuit generates the oscillator control signal by filtering the control signal. A delta-sigma modulator circuit operates to modulate the second signal in response to a modulation profile. As a result, the output clock signal is a spread spectrum clock signal.
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公开(公告)号：US20200313708A1
公开(公告)日：2020-10-01
申请号：US16825887
申请日：2020-03-20
Applicant: STMicroelectronics International N.V.
Inventor： Gagan Midha
IPC: H04B1/12
Abstract: An automatic gain controller for a receiver analog frontend is provided. The automatic gain controller sets a plurality of gains for a plurality of analog frontend stages, respectively. The automatic gain controller detects a first signal level at an output of the analog frontend, determines that the first signal level is saturated and sets a first gain of a first analog frontend stage of the plurality of analog frontend stages to a first coarse gain value based on the first signal level. In response to setting the first gain, the automatic gain controller detects a second signal level at the output of the analog frontend, determines whether the second signal level is saturated and on a condition that the second signal level is not saturated, sets the first gain of the first analog frontend stage to a first fine gain value based on the second signal level.
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公开(公告)号：US10348314B2
公开(公告)日：2019-07-09
申请号：US15888153
申请日：2018-02-05
Applicant: STMicroelectronics International N.V.
Inventor： Anand Kumar , Gagan Midha
Abstract: A phase or frequency locked-loop circuit includes an oscillator configured to generate an output clock signal having a frequency set by an oscillator control signal. A modulator circuit receives a first signal and a second signal and is configured to generate a control signal having a value modulated in response to the first and second signals. A filter circuit generates the oscillator control signal by filtering the control signal. A delta-sigma modulator circuit operates to modulate the second signal in response to a modulation profile. As a result, the output clock signal is a spread spectrum clock signal.
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5.发明申请公开(公告)号：US20180287620A1
公开(公告)日：2018-10-04
申请号：US15471483
申请日：2017-03-28
Applicant: STMicroelectronics International N.V.
Inventor： Gagan Midha , Kallol Chatterjee
Abstract: A phase locked loop (PLL) circuit disclosed herein includes a phase detector receiving a reference frequency signal and a feedback frequency signal, and configured to output a digital signal indicative of a phase difference between the reference frequency signal and the feedback frequency signal. A digital loop filter filters the digital signal. A digital to analog converter converts the filtered digital signal to a control signal. An oscillator generates a PLL clock signal based on the control signal. A sigma-delta modulator modulates a divider signal as a function of a frequency control word. A divider divides the PLL clock signal based on the divider signal, and generates a noisy feedback frequency signal based thereupon. A noise filtering block removes quantization noise from the noisy feedback frequency signal to thereby generate the feedback frequency signal.
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Patent Agency Ranking
公开(公告)号：US11323131B2
公开(公告)日：2022-05-03
申请号：US17089090
申请日：2020-11-04
Applicant: STMicroelectronics International N.V.
Inventor： Gagan Midha , Kallol Chatterjee
Abstract: A delay chain circuit with series coupled delay elements receives a reference clock signal and outputs phase-shifted clock signals. A multiplexer circuit receives the phase-shifted clock signals and selects among the phase-shifted clock signals for output as in response to a selection signal. The selection signal is generated by a control circuit from a periodic signal having a triangular wave profile. A sigma-delta modulator converts the periodic signal to a digital signal, and an integrator circuit integrates the digital signal to output the selection signal. The selected phase-shifted clock signal is applied as the reference signal to a phase locked loop which generates a spread spectrum clock signal.
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公开(公告)号：US10291389B1
公开(公告)日：2019-05-14
申请号：US15923119
申请日：2018-03-16
Applicant: STMicroelectronics International N.V.
Inventor： Gagan Midha
IPC: H03L7/087 , H04L7/033 , H04L7/00 , H03L7/099 , H04B1/7073
Abstract: A modulation circuit includes a locked loop circuit with two-point modulation control and a phase-frequency detector configured to compare a reference frequency signal with a feedback frequency signal. A two-point modulation control circuit includes a first modulation path having a controllable gain and coupled to one of the first and second modulation control points and a second modulation path coupled to another of the first and second modulation control points. Gain matching of the first and second modulation paths is accomplished through the operation of a calibration circuit. The calibration circuit includes a phase detector circuit configured to compare the reference frequency signal with the feedback frequency signal to generate a phase detect signal, and a gain control circuit configured to adjust the controllable gain of the first modulation path as a function a correlation of the phase detect signal with signs of the modulation data.
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公开(公告)号：US20180159544A1
公开(公告)日：2018-06-07
申请号：US15888153
申请日：2018-02-05
Applicant: STMicroelectronics International N.V.
Inventor： Anand Kumar , Gagan Midha
CPC classification number: H03L7/093 , H03C3/095 , H03L7/0891 , H03L7/099 , H03L7/1976 , H04B15/04
Abstract: A phase or frequency locked-loop circuit includes an oscillator configured to generate an output clock signal having a frequency set by an oscillator control signal. A modulator circuit receives a first signal and a second signal and is configured to generate a control signal having a value modulated in response to the first and second signals. A filter circuit generates the oscillator control signal by filtering the control signal. A delta-sigma modulator circuit operates to modulate the second signal in response to a modulation profile. As a result, the output clock signal is a spread spectrum clock signal.
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公开(公告)号：US11296740B2
公开(公告)日：2022-04-05
申请号：US16825887
申请日：2020-03-20
Applicant: STMicroelectronics International N.V.
Inventor： Gagan Midha
IPC: H04B1/12
Abstract: An automatic gain controller for a receiver analog frontend is provided. The automatic gain controller sets a plurality of gains for a plurality of analog frontend stages, respectively. The automatic gain controller detects a first signal level at an output of the analog frontend, determines that the first signal level is saturated and sets a first gain of a first analog frontend stage of the plurality of analog frontend stages to a first coarse gain value based on the first signal level. In response to setting the first gain, the automatic gain controller detects a second signal level at the output of the analog frontend, determines whether the second signal level is saturated and on a condition that the second signal level is not saturated, sets the first gain of the first analog frontend stage to a first fine gain value based on the second signal level.
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公开(公告)号：US11277096B2
公开(公告)日：2022-03-15
申请号：US17175732
申请日：2021-02-15
Applicant: STMicroelectronics International N.V.
Inventor： Gagan Midha , Anurup Mitra , Kallol Chatterjee
Abstract: Disclosed herein is a fine capacitance tuning circuit for a digitally controlled oscillator. The tuning circuit has low and high frequency tuning banks formed by varactors that have their top plates connected to one another. A controller initially sets states of switches selectively connecting the bottom plates of the varactors of the low frequency bank to a low voltage, a high voltage, or to an RC filter, in response to an integer portion of a control word. A sigma-delta modulator initially sets the states of switches selectively connecting the bottom plates of the varactors of the high frequency bank to either the low voltage or the high voltage, in response to a fractional portion of the control word. The controller modifies the states of the switches of the tuning banks in a complementary fashion, based upon comparisons between the fractional portion of the control word and a series of thresholds.
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