- Patent Title: Wireline receiver circuitry having collaborative timing recovery
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Application No.: US15187382Application Date: 2016-06-20
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Publication No.: US09794089B2Publication Date: 2017-10-17
- Inventor: Tawfiq Musah , Gokce Keskin , Ganesh Balamurugan , James E. Jaussi , Bryan K. Casper
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: H04L25/03
- IPC: H04L25/03 ; H04L7/00 ; H04L25/14 ; H04L7/033

Abstract:
Some embodiments include apparatus and methods having an input to receive an input signal, additional inputs to receive clock signals having different phases to sample the input signal, and a decision feedback equalizer (DFE) having DFE slices. The DFE slices include a number of data comparators to provide data information based on the sampling of the input signal, and a number of phase error comparators to provide phase error information associated with the sampling of the input signal. The number of phase error comparators of the DFE slices is not greater than the number of data comparators of the DFE slices.
Public/Granted literature
- US20160301548A1 WIRELINE RECEIVER CIRCUITRY HAVING COLLABORATIVE TIMING RECOVERY Public/Granted day:2016-10-13
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