Invention Grant
- Patent Title: Power switch with source-bias mode for on-chip powerdomain supply drooping
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Application No.: US15236743Application Date: 2016-08-15
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Publication No.: US09798344B2Publication Date: 2017-10-24
- Inventor: Ramakrishnan Venkatasubramanian , Shane Stelmach , Soman Purushotaman , Michael Gill , Jose Luis Flores
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Robert D. Marshall, Jr.; Charles A. Brill; Frank D. Cimino
- Main IPC: G05F1/10
- IPC: G05F1/10 ; G05F3/02 ; H03K17/687

Abstract:
This invention is an electronic circuit with a low power retention mode. A single integrated circuit includes a circuit module and a droop switch circuit supplied by a voltage regulator. In a normal mode a PMOS source-drain channel connects the voltage regulator power to the circuit module power input or isolates them dependent upon a power switch input. In a low power mode a second PMOS connected between the first PMOS gate and output diode connects the first PMOS. This supplied the circuit module from the voltage regulator power as reduced in voltage by a diode forward bias drop. This lower voltage should be sufficient for flip-flops in the circuit module to retain their state while not guaranteeing logic operation. There may be a plurality of chain connected droop switch each powering a corresponding circuit module.
Public/Granted literature
- US20160357211A1 Power Switch with Source-Bias Mode for on-chip Powerdomain Supply Drooping Public/Granted day:2016-12-08
Information query
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