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    Integrated circuit with debugger and arbitration interface
    1.
    发明授权
    Integrated circuit with debugger and arbitration interface 有权

    公开(公告)号：US12204393B2

    公开(公告)日：2025-01-21

    申请号：US18505037

    申请日：2023-11-08

    Applicant: Texas Instruments Incorporated

    Inventor： Jose Luis Flores ,  Gary Augustine Cooper ,  Amritpal Singh Mundra ,  Anthony Lell ,  Jason Lynn Peck

    IPC: G06F11/00 ,  G06F1/3203 ,  G06F11/36

    Abstract: Circuits, systems and methods are provided. A circuit includes a subsystem, an interface, and a debugger. The interface includes power processing and management (PPM) circuitry coupled to the subsystem, and arbitration logic coupled to the PPM circuitry. In operation, the debugger issues a debug request to the arbitration logic to perform a debug operation on the subsystem, and, in response to the debug request, the arbitration logic provides an interrupt associated with the subsystem to the PPM circuitry. The PPM circuitry, in response to the interrupt and a determination that the subsystem is OFF, powers on the subsystem and provides a notification to the arbitration logic indicating that the subsystem is ON. The PPM circuitry also receives a notification from the arbitration logic that the debug operation related to the debug request is complete, and powers off the subsystem in response to that notification.

    Integrated circuit with high-speed clock bypass before reset
    2.
    发明授权
    Integrated circuit with high-speed clock bypass before reset 有权

    公开(公告)号：US11196424B2

    公开(公告)日：2021-12-07

    申请号：US17078708

    申请日：2020-10-23

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Jose Luis Flores ,  Venkateswar Reddy Kowkutla ,  Ramakrishnan Venkatasubramanian

    IPC: H03L7/08 ,  H03K19/20 ,  G06F1/10 ,  G06F1/08 ,  H03K5/00

    Abstract: An integrated circuit includes: a clock domain having a clock domain input; and clock management logic coupled to the clock domain. The clock management logic includes: a PLL having a reference clock input and a PLL clock output; a divider having a divider input and a divider output, the divider input coupled to the PLL clock output; and bypass logic having a first clock input, a second clock input, a bypass control input, and a bypass logic output, the first clock input coupled to divider output, the second clock input coupled to the reference clock input, and the bypass logic output coupled to the clock domain input. The bypass logic selectively bypasses the PLL and divider responsive to a bypass control signal triggered by a reset signal. The reset signal also triggers a reset control signal delayed relative to the bypass control signal.

    Distributed power control for controlling power consumption based on detected activity of logic blocks
    3.
    再颁专利
    Distributed power control for controlling power consumption based on detected activity of logic blocks 有权
    分布式功率控制，用于根据检测到的逻辑块的活动来控制功耗

    公开(公告)号：USRE46193E1

    公开(公告)日：2016-11-01

    申请号：US14303262

    申请日：2014-06-12

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Timothy David Anderson ,  Lewis Nardini ,  Jose Luis Flores ,  Abhijeet Chachad ,  Raguram Damodaran ,  Joseph R. M. Zbiciak ,  Gary Swoboda

    IPC: G06F1/32

    Abstract: An embedded megamodule and an embedded CPU enable power-saving through a combination of hardware and software. The CPU configures the power-down controller (PDC) logic within megamodule and can software trigger a low-power state of logic modules during processor IDLE periods. To wake from this power-down state, a system event is asserted to the CPU through the module interrupt controller. Thus the entry into a low-power state is software-driven during periods of inactivity and power restoration is on system activity that demands the attention of the CPU.

    Abstract translation: 嵌入式巨型模块和嵌入式CPU通过硬件和软件的组合实现节能。 CPU在兆模块内配置掉电控制器（PDC）逻辑，并且可以在处理器空闲周期期间软件触发逻辑模块的低功耗状态。 要从此掉电状态唤醒，系统事件将通过模块中断控制器发送到CPU。 因此，进入低功耗状态是在非活动期间进行软件驱动，并且电源恢复是需要CPU注意的系统活动。

    Distributed mechanism for fine-grained test power control
    5.
    发明授权
    Distributed mechanism for fine-grained test power control 有权

    公开(公告)号：US12217102B2

    公开(公告)日：2025-02-04

    申请号：US17551011

    申请日：2021-12-14

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Devanathan Varadarajan ,  Varun Singh ,  Jose Luis Flores ,  Rejitha Nair ,  David Matthew Thompson

    IPC: G06F9/50 ,  G06F11/30 ,  G06F11/32

    Abstract: An integrated circuit comprises a set of processor cores, wherein each processor core of the set of processor cores includes BIST logic circuitry and multiple memory blocks coupled to the BIST logic circuitry. Each processor core further includes multiple power control circuitry, where each power control circuitry of the multiple power control circuitry is coupled to a respective processor core of the set of processor cores, multiple isolation circuitry, where each isolation circuitry of the multiple isolation circuitry is coupled to a respective processor core of the set of processor cores, a built-in-self repair (BISR) controller coupled to the each of the set of processor cores, each of the multiple power control circuitry, and each of the multiple isolation circuitry, and a safety controller coupled to the BISR controller, the multiple power control circuitry, and to the multiple isolation circuitry.

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