公开(公告)号：US20160357211A1

公开(公告)日：2016-12-08

申请号：US15236743

申请日：2016-08-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ramakrishnan Venkatasubramanian ,  Shane Stelmach ,  Soman Purushotaman ,  Michael Gill ,  Jose Luis Flores

IPC: G05F3/02 ,  H03K17/687

CPC classification number: G05F3/02 ,  H03K17/6871 ,  H03K17/6872

Abstract: This invention is an electronic circuit with a low power retention mode. A single integrated circuit includes a circuit module and a droop switch circuit supplied by a voltage regulator. In a normal mode a PMOS source-drain channel connects the voltage regulator power to the circuit module power input or isolates them dependent upon a power switch input. In a low power mode a second PMOS connected between the first PMOS gate and output diode connects the first PMOS. This supplied the circuit module from the voltage regulator power as reduced in voltage by a diode forward bias drop. This lower voltage should be sufficient for flip-flops in the circuit module to retain their state while not guaranteeing logic operation. There may be a plurality of chain connected droop switch each powering a corresponding circuit module.

Abstract translation: 本发明是具有低功率保持模式的电子电路。 单个集成电路包括由电压调节器提供的电路模块和下垂开关电路。 在正常模式下，PMOS源极 - 漏极通道将电压调节器功率连接到电路模块电源输入，或者根据电源开关输入将其隔离。 在低功率模式中，连接在第一PMOS栅极和输出二极管之间的第二PMOS连接第一PMOS。 这通过二极管正向偏压下降，从电压调节器电源提供电压降低的电压。 这个较低的电压应该足以使电路模块中的触发器保持其状态而不保证逻辑运行。 可以有多个链式连接的下垂开关，各自为对应的电路模块供电。

公开(公告)号：US09798344B2

公开(公告)日：2017-10-24

申请号：US15236743

申请日：2016-08-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ramakrishnan Venkatasubramanian ,  Shane Stelmach ,  Soman Purushotaman ,  Michael Gill ,  Jose Luis Flores

IPC: G05F1/10 ,  G05F3/02 ,  H03K17/687

CPC classification number: G05F3/02 ,  H03K17/6871 ,  H03K17/6872

Abstract: This invention is an electronic circuit with a low power retention mode. A single integrated circuit includes a circuit module and a droop switch circuit supplied by a voltage regulator. In a normal mode a PMOS source-drain channel connects the voltage regulator power to the circuit module power input or isolates them dependent upon a power switch input. In a low power mode a second PMOS connected between the first PMOS gate and output diode connects the first PMOS. This supplied the circuit module from the voltage regulator power as reduced in voltage by a diode forward bias drop. This lower voltage should be sufficient for flip-flops in the circuit module to retain their state while not guaranteeing logic operation. There may be a plurality of chain connected droop switch each powering a corresponding circuit module.

公开(公告)号：US09417648B1

公开(公告)日：2016-08-16

申请号：US14733286

申请日：2015-06-08

Applicant: Texas Instruments Incorporated

Inventor： Ramakrishnan Venkatasubramanian ,  Shane Stelmach ,  Soman Purushotaman ,  Michael Gill ,  Jose Luis Flores

IPC: G05F1/10 ,  G05F3/02 ,  H03K17/687

CPC classification number: G05F3/02 ,  H03K17/6871 ,  H03K17/6872

Abstract: This invention is an electronic circuit with a low power retention mode. A single integrated circuit includes a circuit module and a droop switch circuit supplied by a voltage regulator. In a normal mode a PMOS source-drain channel connects the voltage regulator power to the circuit module power input or isolates them dependent upon a power switch input. In a low power mode a second PMOS connected between the first PMOS gate and output diode connects the first PMOS. This supplied the circuit module from the voltage regulator power as reduced in voltage by a diode forward bias drop. This lower voltage should be sufficient for flip-flops in the circuit module to retain their state while not guaranteeing logic operation. There may be a plurality of chain connected droop switch each powering a corresponding circuit module.

Abstract translation: 本发明是具有低功率保持模式的电子电路。 单个集成电路包括由电压调节器提供的电路模块和下垂开关电路。 在正常模式下，PMOS源极 - 漏极通道将电压调节器功率连接到电路模块电源输入，或者根据电源开关输入将其隔离。 在低功率模式中，连接在第一PMOS栅极和输出二极管之间的第二PMOS连接第一PMOS。 这通过二极管正向偏压下降，从电压调节器电源提供电压降低的电压。 这个较低的电压应该足以使电路模块中的触发器保持其状态而不保证逻辑运行。 可以有多个链式连接的下垂开关，各自为对应的电路模块供电。