- Patent Title: Computation memory operations in a logic layer of a stacked memory
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Application No.: US13724506Application Date: 2012-12-21
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Publication No.: US09804996B2Publication Date: 2017-10-31
- Inventor: James M. O'Connor , Nuwan S. Jayasena , Gabriel H. Loh , Michael Ignatowski , Michael J. Schulte
- Applicant: Advanced Micro Devices, Inc.
- Applicant Address: US CA Sunnyvale
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: Volpe and Koenig, P.C.
- Main IPC: G06F7/38
- IPC: G06F7/38 ; G06F9/00 ; G06F9/44 ; G06F15/78

Abstract:
Some die-stacked memories will contain a logic layer in addition to one or more layers of DRAM (or other memory technology). This logic layer may be a discrete logic die or logic on a silicon interposer associated with a stack of memory dies. Additional circuitry/functionality is placed on the logic layer to implement functionality to perform various computation operations. This functionality would be desired where performing the operations locally near the memory devices would allow increased performance and/or power efficiency by avoiding transmission of data across the interface to the host processor.
Public/Granted literature
- US20140181483A1 Computation Memory Operations in a Logic Layer of a Stacked Memory Public/Granted day:2014-06-26
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