- 专利标题: Digital phase locked loop for low jitter applications
-
申请号: US15248822申请日: 2016-08-26
-
公开(公告)号: US09806723B2公开(公告)日: 2017-10-31
- 发明人: Jingdong Deng , Chung S. Ho , David Flye , Zhenrong Jin , Ramana M. Malladi
- 申请人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 申请人地址: US NY Armonk
- 专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人地址: US NY Armonk
- 代理机构: Roberts Mlotkowski Safran Cole & Calderon, P.C.
- 代理商 Steven Meyers; Andrew M. Calderon
- 主分类号: H03L7/06
- IPC分类号: H03L7/06 ; H03L7/087 ; H03L7/099 ; G06F17/50
摘要:
A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.
公开/授权文献
- US20160365864A1 DIGITAL PHASE LOCKED LOOP FOR LOW JITTER APPLICATIONS 公开/授权日:2016-12-15
信息查询