Invention Grant
- Patent Title: 1T-1R architecture for resistive random access memory
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Application No.: US15206616Application Date: 2016-07-11
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Publication No.: US09824752B2Publication Date: 2017-11-21
- Inventor: Deepak Chandra Sekar , Wayne Frederick Ellis
- Applicant: Rambus Inc.
- Applicant Address: US CA Sunnyvale
- Assignee: Rambus Inc.
- Current Assignee: Rambus Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: Lowenstein Sandler LLP
- Main IPC: G11C13/00
- IPC: G11C13/00 ; G11C11/419 ; G11C11/16 ; G11C5/06 ; G11C5/02
Abstract:
A memory device includes an array of resistive memory cells wherein each pair of resistive memory cells includes a first switching element electrically coupled in series to a first resistive memory element and a second switching element electrically coupled in series to a second resistive memory element. A source of the first switching element and a source of the second switching element receive a common source line signal.
Public/Granted literature
- US20170004879A1 1T-1R ARCHITECTURE FOR RESISTIVE RANDOM ACCESS MEMORY Public/Granted day:2017-01-05
Information query
