Invention Grant
- Patent Title: Resistance mitigation in physical design
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Application No.: US14981449Application Date: 2015-12-28
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Publication No.: US09871039B2Publication Date: 2018-01-16
- Inventor: Jean-Luc Pelloie , Marlin Wayne Frederick, Jr.
- Applicant: ARM Limited
- Applicant Address: GB Cambridge
- Assignee: ARM Limited
- Current Assignee: ARM Limited
- Current Assignee Address: GB Cambridge
- Agency: Pramudji Law Group PLLC
- Agent Ari Pramudji
- Main IPC: H01L21/70
- IPC: H01L21/70 ; H01L27/088 ; H01L25/00 ; G06F17/50 ; H01L27/092 ; H01L21/8238 ; H01L23/522 ; H01L23/528 ; H01L27/02

Abstract:
Various implementations described herein are directed to an integrated circuit with mitigated resistance. The integrated circuit may include a cell having a plurality of transistors including a first transistor of a first type and a second transistor of a second type that is different from the first type. The integrated circuit may include a first wire coupling the first transistor to the second transistor. The integrated circuit may include a second wire coupling the first wire to an output routing wire. The integrated circuit may include a redundant wire further coupling the first wire to the output routing wire.
Public/Granted literature
- US20170186745A1 Resistance Mitigation in Physical Design Public/Granted day:2017-06-29
Information query
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