公开(公告)号：US20220199527A1

公开(公告)日：2022-06-23

申请号：US17125704

申请日：2020-12-17

Applicant: Arm Limited

Inventor： Jean-Luc Pelloie

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/02 ,  G06F30/3953

Abstract: According to one implementation of the present disclosure, a power grid comprising: one or more cells; a metal layer; first and second buried power rails; and one or more local interconnects, wherein one or more local interconnect stitches are configured to electrically couple the one or more cells to either of the first or second buried power rails through the metal layer and the one or more local interconnects.

公开(公告)号：US09734269B2

公开(公告)日：2017-08-15

申请号：US14736028

申请日：2015-06-10

Applicant: ARM Limited

Inventor： Jean-Luc Pelloie ,  Kenza Charafeddine

IPC: G06F17/50 ,  G06F9/455

CPC classification number: G06F17/5036 ,  G06F17/5031 ,  G06F2217/84

Abstract: Various implementations described herein are directed to a system and methods for generating timing data for an integrated circuit. In one implementation, the method may include generating first timing data for the integrated circuit, and the first timing data may be related to one or more variations of operating conditions for the integrated circuit. Further, the method may include extracting parameter values from the first timing data in association with the one or more variations of operating conditions. Further, the method may include generating second timing data for the integrated circuit, and the second timing data may be based on the extracted parameter values.

公开(公告)号：US20170186745A1

公开(公告)日：2017-06-29

申请号：US14981449

申请日：2015-12-28

Applicant: ARM Limited

Inventor： Jean-Luc Pelloie ,  Marlin Wayne Frederick, JR.

IPC: H01L27/092 ,  H01L21/8238 ,  H01L27/02 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L27/092 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207

Abstract: Various implementations described herein are directed to an integrated circuit with mitigated resistance. The integrated circuit may include a cell having a plurality of transistors including a first transistor of a first type and a second transistor of a second type that is different from the first type. The integrated circuit may include a first wire coupling the first transistor to the second transistor. The integrated circuit may include a second wire coupling the first wire to an output routing wire. The integrated circuit may include a redundant wire further coupling the first wire to the output routing wire.

公开(公告)号：US20250079311A1

公开(公告)日：2025-03-06

申请号：US18950866

申请日：2024-11-18

Applicant: Arm Limited

Inventor： Jean-Luc Pelloie

IPC: H01L23/528 ,  G06F30/3953 ,  H01L23/522 ,  H01L27/02

Abstract: According to one implementation of the present disclosure, a power grid comprising: one or more cells; a metal layer; first and second buried power rails; and one or more local interconnects, wherein one or more local interconnect stitches are configured to electrically couple the one or more cells to either of the first or second buried power rails through the metal layer and the one or more local interconnects.

公开(公告)号：US10452804B2

公开(公告)日：2019-10-22

申请号：US15447716

申请日：2017-03-02

Applicant: ARM Limited

Inventor： Jean-Luc Pelloie

IPC: G06F17/50

Abstract: A computer implemented method is described for generating a layout of a circuit block of an integrated circuit. The method comprises receiving input data defining a logical operation of the circuit block, and accessing a cell library providing a plurality of cells that define circuit elements, in order to determine with reference to the input data the cells to be used to implement the circuit block. A place and route tool is then employed to generate the layout by determining a placement of the determined cells and performing a routing operation to determine routing paths to be provided within a plurality of metal layers in order to interconnect the determined cells. The cell library provides cells that define in at least one metal layer one or more superfluous metal sections that are required to comply with design rules but which are unused by the cell. Each cell has cell definition data, and the cell definition data of one or more cells is arranged to identify at least one superfluous metal section as being available for routing. During performance of the routing operation, the place and route tool then references the cell definition data of the determined cells so as to take into account, when determining the routing paths, availability of any superfluous metal sections for routing. This can significantly increase the options available to the place and route tool when determining the appropriate routing paths.

公开(公告)号：US12148697B2

公开(公告)日：2024-11-19

申请号：US17125704

申请日：2020-12-17

Applicant: Arm Limited

Inventor： Jean-Luc Pelloie

IPC: H01L23/528 ,  G06F30/3953 ,  H01L23/522 ,  H01L27/02 ,  H01L27/118

Abstract: According to one implementation of the present disclosure, a power grid comprising: one or more cells; a metal layer; first and second buried power rails; and one or more local interconnects, wherein one or more local interconnect stitches are configured to electrically couple the one or more cells to either of the first or second buried power rails through the metal layer and the one or more local interconnects.

公开(公告)号：US09871039B2

公开(公告)日：2018-01-16

申请号：US14981449

申请日：2015-12-28

Applicant: ARM Limited

Inventor： Jean-Luc Pelloie ,  Marlin Wayne Frederick, Jr.

IPC: H01L21/70 ,  H01L27/088 ,  H01L25/00 ,  G06F17/50 ,  H01L27/092 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02

CPC classification number: H01L27/092 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207

Abstract: Various implementations described herein are directed to an integrated circuit with mitigated resistance. The integrated circuit may include a cell having a plurality of transistors including a first transistor of a first type and a second transistor of a second type that is different from the first type. The integrated circuit may include a first wire coupling the first transistor to the second transistor. The integrated circuit may include a second wire coupling the first wire to an output routing wire. The integrated circuit may include a redundant wire further coupling the first wire to the output routing wire.

公开(公告)号：US20160364517A1

公开(公告)日：2016-12-15

申请号：US14736028

申请日：2015-06-10

Applicant: ARM Limited

Inventor： Jean-Luc Pelloie ,  Kenza Charafeddine

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5031 ,  G06F2217/84

Abstract: Various implementations described herein are directed to a system and methods for generating timing data for an integrated circuit. In one implementation, the method may include generating first timing data for the integrated circuit, and the first timing data may be related to one or more variations of operating conditions for the integrated circuit. Further, the method may include extracting parameter values from the first timing data in association with the one or more variations of operating conditions. Further, the method may include generating second timing data for the integrated circuit, and the second timing data may be based on the extracted parameter values.

Abstract translation: 这里描述的各种实现涉及用于生成集成电路的定时数据的系统和方法。 在一个实现中，该方法可以包括为集成电路产生第一定时数据，并且第一定时数据可以与集成电路的一个或多个操作条件的变化有关。 此外，该方法可以包括与操作条件的一个或多个变化相关联地从第一定时数据提取参数值。 此外，该方法可以包括产生用于集成电路的第二定时数据，并且第二定时数据可以基于所提取的参数值。

公开(公告)号：US08959472B1

公开(公告)日：2015-02-17

申请号：US14039224

申请日：2013-09-27

Applicant: ARM Limited

Inventor： Marlin Wayne Frederick, Jr. ,  Jean-Luc Pelloie

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5077

Abstract: A method of generating an integrated circuit layout comprises a step of determining a placement of standard cells selected from a standard cell library while permitting boundary conflicts in which incompatible boundary regions of standard cells are placed next to each other. After determining routing connections between the standard cells, the integrated circuit layout is generated. The generation of the integrated circuit layout includes a mapping step of mapping at least one incompatible boundary region to an alternative boundary region to resolve at least one boundary conflict.

Abstract translation: 一种生成集成电路布局的方法包括以下步骤：确定从标准单元库选择的标准单元的放置，同时允许标准单元的不兼容边界区域彼此相邻放置的边界冲突。 在确定标准单元之间的路由连接之后，生成集成电路布局。 集成电路布局的生成包括将至少一个不兼容的边界区域映射到替代边界区域以解决至少一个边界冲突的映射步骤。