Invention Grant
- Patent Title: Method for managing a fail row of the memory plane of a non volatile memory and corresponding memory device
-
Application No.: US15140856Application Date: 2016-04-28
-
Publication No.: US09875798B2Publication Date: 2018-01-23
- Inventor: Francesco La Rosa , Gineuve Alieri
- Applicant: STMicroelectronics (Rousset) SAS
- Applicant Address: FR Rousset
- Assignee: STMicroelectronics (Rousset) SAS
- Current Assignee: STMicroelectronics (Rousset) SAS
- Current Assignee Address: FR Rousset
- Agency: Slater Matsil, LLP
- Priority: FR1561730 20151202
- Main IPC: G11C14/00
- IPC: G11C14/00 ; G11C16/16 ; G11C29/00 ; G11C16/10 ; G11C16/26

Abstract:
A non-volatile memory is erasable by page and equipped with a row redundancy mechanism. In the case of the detection of a defective row of the memory plane, the storing of the address of the row in a non-volatile register is carried out and a redundant row having a new address is assigned. In the case of an attempt to write to the defective row, a write to the redundant row is carried out. When writing to the redundant row, the new content of the redundant row is loaded into a volatile memory and, following an operation for writing to any other row of the memory plane, a re-loading of the new content of the redundant row into the volatile memory.
Public/Granted literature
Information query