Invention Grant
- Patent Title: Method for manufacturing transistor with SiCN/SiOCN multilayer spacer
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Application No.: US15592150Application Date: 2017-05-10
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Publication No.: US09882022B2Publication Date: 2018-01-30
- Inventor: Chia-Ming Kuo , Po-Jen Chuang , Fu-Jung Chuang , Tsai-Yu Wen , Tsuo-Wen Lu , Yu-Ren Wang , Fu-Yu Tsai
- Applicant: UNITED MICROELECTRONICS CORP.
- Applicant Address: TW Hsin-Chu
- Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee Address: TW Hsin-Chu
- Agent Winston Hsu
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L21/02 ; H01L21/311 ; H01L21/28 ; H01L29/49 ; H01L29/08 ; H01L29/16 ; H01L29/161 ; H01L29/165 ; H01L29/78
Abstract:
A semiconductor device and a method for manufacturing the same are provided in the present invention. The semiconductor device includes a substrate, a gate structure on the substrate and two spacers on both sidewalls of the gate structure. Each spacer comprises an inner first spacer portion made of SiCN and an outer second spacer portion made of SiOCN.
Public/Granted literature
- US20170243952A1 METHOD FOR MANUFACTURING TRANSISTOR WITH SICN/SIOCN MULTILAYER SPACER Public/Granted day:2017-08-24
Information query
IPC分类:
