- 专利标题： Metal line connection for improved RRAM reliability, semiconductor arrangement comprising the same, and manufacture thereof
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申请号： US15292334申请日： 2016-10-13
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公开(公告)号： US09893122B2公开(公告)日： 2018-02-13
- 发明人: Chun-Yang Tsai , Yu-Wei Ting , Kuo-Ching Huang
- 申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 申请人地址： TW Hsin-Chu
- 专利权人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人地址： TW Hsin-Chu
- 代理机构： Eschweiler & Potashnik, LLC
- 主分类号： G11C11/00
- IPC分类号： G11C11/00 ; H01L27/24 ; G11C13/00 ; H01L23/528 ; H01L45/00 ; H01L27/10
摘要：
Some embodiments relate to an integrated circuit device including an array of memory cells disposed over a semiconductor substrate. An array of first metal lines are disposed at a first height over the substrate and are connected to the memory cells of the array. Each of the first metal lines has a first cross-sectional area. An array of second metal lines are disposed at a second height over the substrate and are connected to the memory cells of the array. Each of the second metal lines has a second cross-sectional area which is greater than the first cross-sectional area.
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