Invention Grant
- Patent Title: Memory interface with adjustable voltage and termination and methods of use
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Application No.: US14863890Application Date: 2015-09-24
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Publication No.: US09910482B2Publication Date: 2018-03-06
- Inventor: Michael Brunolli , Stephen Thilenius , Patrick Isakanian , Vaishnav Srinivas
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Haynes and Boone, LLP
- Main IPC: G06F1/32
- IPC: G06F1/32 ; G11C7/10 ; G11C11/4074 ; G06F13/16 ; G06F13/40 ; G06F13/42 ; H04L25/02

Abstract:
A memory interface includes: a pull-up device and a pull-down device, wherein the pull-up device couples between a power rail and a data line, and wherein the pull-down device couples between the data line and ground; and a power supply configured to supply a first power supply voltage to the power rail during a terminated data transmission mode in which a receiving memory interface coupled to the data line has an active on-die termination, and wherein the power supply is further configured to supply a second power supply voltage to the power rail during an unterminated data transmission mode in which the on-die termination does not load the data line, the second power supply voltage being less than the first power supply voltage.
Public/Granted literature
- US20170090546A1 MEMORY INTERFACE WITH ADJUSTABLE VOLTAGE AND TERMINATION AND METHODS OF USE Public/Granted day:2017-03-30
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