A semiconductor device includes a substrate having source and drain regions, and a channel region arranged between the source and drain regions. The device further includes a gate structure over the substrate and adjacent to the channel region. The gate structure includes a gate stack, a spacer on sidewalls of the gate stack, and a conductor over the gate stack. The device further includes a first contact feature over the substrate and electrically connecting to at least one of the source and drain regions. A top surface of the first contact feature is lower than a top surface of the gate structure. The device further includes a first dielectric layer over the first contact feature. A top surface of the first dielectric layer is below or substantially co-planar with the top surface of the gate structure. The conductor at most partially overlaps in plan view with the first dielectric layer.