公开(公告)号：US11682671B2

公开(公告)日：2023-06-20

申请号：US17037447

申请日：2020-09-29

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Wei-Ling Chang ,  Lee-Chung Lu ,  Xiangdong Chen ,  Kam-Tou Sio ,  Hsiang-Chi Huang

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L23/528 ,  H01L29/08 ,  H01L21/28 ,  H01L29/49

CPC分类号： H01L27/092 ,  H01L21/28123 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/528 ,  H01L29/0847 ,  H01L29/4916

摘要： An integrated circuit structure includes a first transistor, a second transistor, a first conductive via, a second conductive via, and a connection line. The first transistor includes a first active region, a first gate electrode over the first active region; and a first channel in the first active region and under the first gate electrode. The second transistor includes a second active region, a second gate electrode over the second active region, and a second channel in the second active region and under the second gate electrode. The first conductive via is electrically connected to the first gate electrode. The second conductive via is electrically connected to the second gate electrode. The connection line electrically connects the first and second conductive vias. The first transistor and the first conductive via and the second transistor and the second conductive via are arranged mirror-symmetrically with respect to a symmetry plane.

公开(公告)号：US11658182B2

公开(公告)日：2023-05-23

申请号：US17209730

申请日：2021-03-23

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Kam-Tou Sio ,  Shang-Wei Fang ,  Jiann-Tyng Tzeng ,  Chew-Yuen Young

IPC分类号： H01L23/498 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L27/0886 ,  H01L21/823821 ,  H01L23/49827 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

摘要： An integrated circuit device includes: a first fin structure disposed on a substrate in a first direction; a second fin structure disposed on the substrate and aligned in the first direction; a third fin structure disposed on the substrate and aligned in the first direction; and a first conductive line aligned in a second direction arranged to wrap a first portion, a second portion, and a third portion of the first fin structure, the second fin structure and the third fin structure, respectively. Each of the first fin structure, the second fin structure and the third fin structure has a same type dopant. A first distance between the first fin structure and the second fin structure is different from a second distance between the second fin structure and the third fin structure.

公开(公告)号：US11437998B2

公开(公告)日：2022-09-06

申请号：US17186256

申请日：2021-02-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Kam-Tou Sio ,  Jiun-Wei Lu

IPC分类号： H03K19/17736 ,  H03K19/17784 ,  G06F1/10

摘要： An integrated circuit is disclosed, including a first latch circuit, a second latch circuit, and a clock circuit. The first latch circuit transmits multiple data signals to the second latch circuit through multiple first conductive lines disposed on a front side of the integrated circuit. The clock circuit transmits a first clock signal and a second clock signal to the first latch circuit and the second latch circuit through multiple second conductive lines disposed on a backside, opposite of the front side, of the integrated circuit.

公开(公告)号：US11270936B2

公开(公告)日：2022-03-08

申请号：US16530770

申请日：2019-08-02

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Kam-Tou Sio ,  Jiann-Tyng Tzeng ,  Wei-Cheng Lin

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/528

摘要： An integrated circuit includes a substrate and a first conductive line extending in a first direction parallel to a top surface of the substrate, wherein the first conductive line is a first distance from the top surface of the substrate. The integrated circuit further includes a second conductive line extending in a second direction parallel to the top surface of the substrate, wherein the second conductive line is a second distance from the top surface of the substrate, and the second distance is greater than the first distance. The integrated circuit further includes a third conductive line extending in the first direction, wherein the second conductive line is a third distance from the top surface of the substrate, and the third distance is greater than the second distance. The integrated circuit further includes a supervia directly connected to the first conductive line and the third conductive line.

公开(公告)号：US10366200B2

公开(公告)日：2019-07-30

申请号：US15258932

申请日：2016-09-07

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Wei-Cheng Lin ,  Chih-Liang Chen ,  Chih-Ming Lai ,  Charles Chew-Yuen Young ,  Jiann-Tyng Tzeng ,  Kam-Tou Sio ,  Ru-Gun Liu ,  Shih-Wei Peng ,  Wei-Chen Chien

IPC分类号： G06F17/50

摘要： A method of forming a layout design for fabricating an integrated circuit is disclosed. The method includes generating a first layout of the integrated circuit based on design criteria, generating a standard cell layout of the integrated circuit, generating a via color layout of the integrated circuit based on the first layout and the standard cell layout and performing a color check on the via color layout based on design rules. The first layout having a first set of vias arranged in first rows and first columns. The standard cell layout having standard cells and a second set of vias arranged in the standard cells. The via color layout having a third set of vias. The third set of vias including a portion of the second set of vias and corresponding locations, and color of corresponding sub-set of vias.

公开(公告)号：US09917050B2

公开(公告)日：2018-03-13

申请号：US15331363

申请日：2016-10-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Liang Chen ,  Chih-Ming Lai ,  Kam-Tou Sio ,  Ru-Gun Liu ,  Meng-Hung Shen ,  Chun-Hung Liou ,  Shu-Hui Sung ,  Charles Chew-Yuen Young

IPC分类号： G01R31/26 ,  H01L23/522 ,  H01L21/768 ,  H01L23/535 ,  H01L23/48 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/532 ,  H01L27/088 ,  H01L29/40 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66

CPC分类号： H01L23/5226 ,  H01L21/768 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76879 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/48 ,  H01L23/5283 ,  H01L23/5329 ,  H01L23/535 ,  H01L27/088 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66583 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a substrate having source and drain regions, and a channel region arranged between the source and drain regions. The device further includes a gate structure over the substrate and adjacent to the channel region. The gate structure includes a gate stack, a spacer on sidewalls of the gate stack, and a conductor over the gate stack. The device further includes a first contact feature over the substrate and electrically connecting to at least one of the source and drain regions. A top surface of the first contact feature is lower than a top surface of the gate structure. The device further includes a first dielectric layer over the first contact feature. A top surface of the first dielectric layer is below or substantially co-planar with the top surface of the gate structure. The conductor at most partially overlaps in plan view with the first dielectric layer.

公开(公告)号：US20170040259A1

公开(公告)日：2017-02-09

申请号：US15331363

申请日：2016-10-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Liang Chen ,  Chih-Ming Lai ,  Kam-Tou Sio ,  Ru-Gun Liu ,  Meng-Hung Shen ,  Chun-Hung Liou ,  Shu-Hui Sung ,  Charles Chew-Yuen Young

IPC分类号： H01L23/522 ,  H01L29/423 ,  H01L29/45 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/40 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L23/5226 ,  H01L21/768 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76879 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/48 ,  H01L23/5283 ,  H01L23/5329 ,  H01L23/535 ,  H01L27/088 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66583 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a substrate having source and drain regions, and a channel region arranged between the source and drain regions. The device further includes a gate structure over the substrate and adjacent to the channel region. The gate structure includes a gate stack, a spacer on sidewalls of the gate stack, and a conductor over the gate stack. The device further includes a first contact feature over the substrate and electrically connecting to at least one of the source and drain regions. A top surface of the first contact feature is lower than a top surface of the gate structure. The device further includes a first dielectric layer over the first contact feature. A top surface of the first dielectric layer is below or substantially co-planar with the top surface of the gate structure. The conductor at most partially overlaps in plan view with the first dielectric layer.

摘要翻译： 半导体器件包括具有源区和漏区的衬底以及布置在源区和漏区之间的沟道区。 该器件还包括在衬底上并与沟道区相邻的栅极结构。 栅极结构包括栅极堆叠，栅极堆叠的侧壁上的间隔物和栅极堆叠上的导体。 该器件还包括在衬底上的第一接触特征，并且电连接到源区和漏区中的至少一个。 第一接触特征的顶表面低于栅极结构的顶表面。 该装置还包括在第一接触特征上的第一介电层。 第一电介质层的顶表面与栅极结构的顶表面低于或基本上共平面。 导体在与第一介电层的平面图中最多部分重叠。

公开(公告)号：US12039246B2

公开(公告)日：2024-07-16

申请号：US18325501

申请日：2023-05-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Wei Peng ,  Kam-Tou Sio ,  Jiann-Tyng Tzeng

IPC分类号： G06F30/392 ,  G06F30/394 ,  G06F30/396

CPC分类号： G06F30/392 ,  G06F30/394 ,  G06F30/396

摘要： Generating a circuit layout is provided. A circuit layout associated with a circuit is received. A parallel pattern recognition is performed on the circuit layout. Performing the parallel pattern recognition includes determining that there is a parallel pattern in the circuit layout. In response to determining that there is a parallel pattern in the circuit layout, a cell swap for a first cell associated with the parallel pattern with a second cell is performed. After the cell swap for the first cell, engineering change order routing is performed to connect the second cell in the circuit layout. An updated circuit layout having the second cell is provided.

公开(公告)号：US11935825B2

公开(公告)日：2024-03-19

申请号：US16554035

申请日：2019-08-28

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Kam-Tou Sio ,  Cheng-Chi Chuang ,  Chih-Ming Lai ,  Jiann-Tyng Tzeng ,  Wei-Cheng Lin ,  Lipen Yuan

IPC分类号： H01L23/522 ,  G06F30/394 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092

CPC分类号： H01L23/5221 ,  G06F30/394 ,  H01L21/76805 ,  H01L21/76837 ,  H01L21/76877 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/5286 ,  H01L27/0924

摘要： An IC structure includes a fin structure, a contact overlying the fin structure along a first direction, and an isolation layer between the contact and the fin structure. The isolation layer is adjacent to a portion of the contact along a second direction perpendicular to the first direction.

公开(公告)号：US11916070B2

公开(公告)日：2024-02-27

申请号：US17345452

申请日：2021-06-11

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Te-Hsin Chiu ,  Kam-Tou Sio ,  Shang-Wei Fang ,  Wei-Cheng Lin ,  Jiann-Tyng Tzeng

IPC分类号： H01L27/088 ,  H01L29/06 ,  G06F30/392 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/033 ,  H01L29/66

CPC分类号： H01L27/0886 ,  G06F30/392 ,  H01L21/0334 ,  H01L21/823431 ,  H01L29/0665 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

摘要： Disclosed are semiconductor devices including a substrate, a first transistor formed over a first portion of the substrate, wherein the first transistor comprises a first nanosheet stack including N nanosheets and a second transistor over a second portion of the substrate, wherein the second transistor comprises a second nanosheet stack including M nanosheets, wherein N is different from M in which the first and second nanosheet stacks are formed on first and second substrate regions that are vertically offset from one another.