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1.发明授权公开(公告)号：US11688730B2
公开(公告)日：2023-06-27
申请号：US17225664
申请日：2021-04-08
发明人： Kam-Tou Sio , Chih-Liang Chen , Hui-Ting Yang , Shun Li Chen , Ko-Bin Kao , Chih-Ming Lai , Ru-Gun Liu , Charles Chew-Yuen Young
IPC分类号： H01L27/02 , H01L21/3213 , H01L21/8234 , H01L27/088 , H01L29/417 , H01L29/423 , H01L27/11
CPC分类号： H01L27/0207 , H01L21/32133 , H01L21/32139 , H01L21/823431 , H01L21/823475 , H01L27/0886 , H01L29/41791 , H01L29/42376 , H01L21/823437 , H01L27/1104 , H01L27/1116
摘要： A system that generates a layout diagram has a processor that implements a method, the method including: generating first and second conductor shapes; generating first, second and third cap shapes correspondingly over the first and second conductor shapes; arranging a corresponding one of the second conductor shapes to be interspersed between each pair of neighboring ones of the first conductor shapes; generating first cut patterns over selected portions of corresponding ones of the first cap shapes; and generating second cut patterns over selected portions of corresponding ones of the second cap shapes. In some circumstances, the first cut patterns are designated as selective for a first etch sensitivity corresponding to the first cap shapes; and the second cut patterns are designated as selective for a second etch sensitivity corresponding to the second cap shapes.
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公开(公告)号：US11616067B2
公开(公告)日：2023-03-28
申请号：US17552433
申请日：2021-12-16
发明人： Chih-Liang Chen , Chih-Ming Lai , Charles Chew-Yuen Young , Chin-Yuan Tseng , Jiann-Tyng Tzeng , Kam-Tou Sio , Ru-Gun Liu , Wei-Liang Lin , L. C. Chou
IPC分类号： H01L21/8234 , H01L27/11 , H01L27/088 , H01L21/308 , H01L29/78 , H01L29/66 , H01L21/311
摘要： In an embodiment, a method (of manufacturing fins for a semiconductor device) includes: forming a first layer (on a semiconductor substrate) that has first spacers and etch stop layer (ESL) portions which are interspersed; forming second spacers on central regions of the first spacers and the ESL portions; removing exposed regions of the first spacers and the ESL portions and corresponding underlying portions of the semiconductor substrate; removing the second spacers resulting in corresponding first capped semiconductor fins and second capped semiconductor fins that are organized into first and second sets; each member of the first set having a first cap with a first etch sensitivity; and each member of the second set having a second cap with a different second etch sensitivity; and eliminating selected ones of the first capped semiconductor fins and selected ones of the second capped semiconductor fins.
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3.发明申请公开(公告)号：US20220068342A1
公开(公告)日：2022-03-03
申请号：US17524125
申请日：2021-11-11
发明人： Jack Liu , Charles Chew-Yuen Young
摘要： Some embodiments of the present disclosure relate to a memory device. The memory device includes an active current path including a data storage element; and a reference current path including a reference resistance element. The reference resistance element has a resistance that differs from a resistance of the data storage element. A delay-sensing element has a first input coupled to the active current path and a second input coupled to the reference current path. The delay-sensing element is configured to sense a timing delay between a first signal on the active current path and a second signal on the reference current path. The delay-sensing element is further configured to determine a data state stored in the data storage element based on the timing delay.
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公开(公告)号：US11127626B2
公开(公告)日：2021-09-21
申请号：US17033759
申请日：2020-09-26
IPC分类号： H01L21/00 , H01L21/768 , H01L21/033 , H01L21/02
摘要： A method of manufacturing a semiconductor device includes providing a wafer having a first surface, wherein the wafer includes a gate electrode having a top surface, and the top surface is leveled with the first surface; and forming an alignment structure on the top surface. The method further includes forming a photoresist on the alignment layer to cover a portion of the top surface; and removing portions of the alignment layer uncovered by the photoresist to form an alignment structure on the top surface. The method further includes forming a dielectric surrounding the alignment structure on the first surface and over the alignment structure, removing a portion of the dielectric to expose the alignment structure by CMP; removing the alignment structure to expose at least a portion of the top surface of the gate electrode, and forming a gate conductor over and in contact with the gate electrode.
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公开(公告)号：US10796947B2
公开(公告)日：2020-10-06
申请号：US16217469
申请日：2018-12-12
IPC分类号： H01L21/00 , H01L21/768 , H01L21/033 , H01L21/02
摘要： A method of manufacturing a semiconductor device includes providing a wafer having a first surface, wherein the wafer includes a gate electrode having a top surface, and the top surface of the gate electrode is substantially level with the first surface; and forming an alignment structure on the top surface of the gate electrode. The method further includes forming a dielectric surrounding the alignment structure on the first surface, removing the alignment structure to expose at least a portion of the top surface of the gate electrode, and forming a gate conductor over and in contact with the gate electrode.
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公开(公告)号：US10388644B2
公开(公告)日：2019-08-20
申请号：US15676225
申请日：2017-08-14
发明人： Kam-Tou Sio , Chih-Liang Chen , Chih-Ming Lai , Charles Chew-Yuen Young , Hui-Ting Yang , Ko-Bin Kao , Ru-Gun Liu , Shun Li Chen
IPC分类号： H01L21/3065 , H01L27/02 , H01L21/3213 , H01L21/8234 , H01L27/088 , H01L29/417 , H01L29/423 , H01L27/11
摘要： A method of manufacturing conductors for a semiconductor device, the method comprising: forming a structure on a base; and eliminating selected portions of members of a first set and selected portions of members of a second set from the structure. The structure includes: capped first conductors arranged parallel to a first direction; and capped second conductors arranged parallel to and interspersed with the capped first conductors. The capped first conductors are organized into at least first and second sets. Each member of the first set has a first cap with a first etch sensitivity. Each member of the second set has a second cap with a second etch sensitivity. Each of the capped second conductors has a third etch sensitivity. The first, second and third etch sensitivities are different.
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公开(公告)号：US20190065658A1
公开(公告)日：2019-02-28
申请号：US15966693
申请日：2018-04-30
发明人： Shih-Wei PENG , Chih-Liang Chen , Charles Chew-Yuen Young , Hui-Zhong Zhuang , Jiann-Tyng Tzeng , Shun Li Chen , Wei-Cheng Lin
摘要： A method of forming an integrated circuit includes generating, by a processor, a layout design of the integrated circuit based on a set of design rules and manufacturing the integrated circuit based on the layout design. The integrated circuit has a first gate. Generating the layout design includes generating a set of gate layout patterns, generating a cut feature layout pattern and generating a first via layout pattern. The cut feature layout pattern extends in a first direction, is located on the first layout level and overlaps at least a first gate layout pattern. The set of gate layout patterns extends in a second direction and is located on a first layout level. The first via layout pattern is over the first gate layout pattern, and is separated in the second direction from the cut feature layout pattern by a first distance. The first distance satisfies a first design rule.
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8.发明申请CLOCK GATING CIRCUITS AND CIRCUIT ARRANGEMENTS INCLUDING CLOCK GATING CIRCUITS 审中-公开时钟增益电路和电路安排，包括时钟增益电路公开(公告)号：US20160077544A1
公开(公告)日：2016-03-17
申请号：US14488588
申请日：2014-09-17
IPC分类号： G06F1/08
CPC分类号： G06F1/10
摘要： Clock gating circuits may include: a first inverter; a first switch having a first terminal and a second terminal, the first terminal of the first switch coupled to an output of the first inverter; a feedback circuit having an input-output terminal, the input-output terminal of the feedback circuit coupled to the second terminal of the first switch; and a first logic gate having a first input terminal and a second input terminal, the first input terminal coupled to the input-output terminal of the feedback circuit, the second input terminal electrically connected to receive a master clock signal.
摘要翻译： 时钟选通电路可以包括：第一反相器; 具有第一端子和第二端子的第一开关，所述第一开关的第一端子耦合到所述第一反相器的输出; 具有输入输出端子的反馈电路，所述反馈电路的输入输出端子耦合到所述第一开关的第二端子; 以及具有第一输入端和第二输入端的第一逻辑门，所述第一输入端耦合到所述反馈电路的输入输出端，所述第二输入端电连接以接收主时钟信号。
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公开(公告)号：US20210366844A1
公开(公告)日：2021-11-25
申请号：US17393619
申请日：2021-08-04
发明人： Kam-Tou Sio , Chih-Ming Lai , Chun-Kuang Chen , Chih-Liang Chen , Charles Chew-Yuen Young , Chi-Yeh Yu , Jiann-Tyng Tzeng , Ru-Gun Liu , Wen-Hao Chen
IPC分类号： H01L23/00 , H01L23/528 , H01L23/522 , H01L23/485
摘要： The present disclosure relates to an integrated chip. The integrated chip includes a plurality of gate structures arranged over a substrate and between adjacent ones of a plurality of source/drain regions within the substrate. A plurality of conductive contacts are electrically coupled to the plurality of source/drain regions. A first interconnect wire is arranged over the plurality of conductive contacts, and a second interconnect wire arranged over the first interconnect wire. A via rail contacts the first interconnect wire and the second interconnect wire. The via rail has an outer sidewall that faces an outermost edge of the plurality of source/drain regions and that is laterally separated from the outermost edge of the plurality of source/drain regions by a non-zero distance. The outer sidewall of the via rail continuously extends past two or more of the plurality of gate structures.
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公开(公告)号：US10977421B2
公开(公告)日：2021-04-13
申请号：US16793693
申请日：2020-02-18
发明人： Wei-Cheng Lin , Chih-Liang Chen , Chih-Ming Lai , Charles Chew-Yuen Young , Jiann-Tyng Tzeng , Kam-Tou Sio , Ru-Gun Liu , Shih-Wei Peng , Wei-Chen Chien
IPC分类号： G06F30/30 , G06F30/398 , G06F30/392
摘要： A method of manufacturing an integrated circuit includes generating a first layout design based on design criteria, performing a color mapping between the first layout design and a standard cell layout design thereby generating a via color layout design, and manufacturing the integrated circuit based on the via color layout design. The first layout design has a first set of vias divided into sub-sets of vias based on a corresponding color indicating that vias of the sub-set of vias with a same color, and vias of the sub-set of vias with a different color. The standard cell layout design has a second set of vias arranged in standard cells. The via color layout design has a third set of vias including a portion of the second set of vias and corresponding locations, and color of the corresponding sub-set of vias.
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