Invention Grant
- Patent Title: Erase stress and delta erase loop count methods for various fail modes in non-volatile memory
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Application No.: US14528711Application Date: 2014-10-30
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Publication No.: US09934872B2Publication Date: 2018-04-03
- Inventor: Sagar Magia , Jagdish Sabde , Jayavel Pachamuthu
- Applicant: SANDISK TECHNOLOGIES LLC
- Applicant Address: US TX Plano
- Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee Address: US TX Plano
- Agency: Foley & Lardner LLP
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G11C29/52 ; G06F3/06 ; G11C16/34 ; G11C29/06 ; G11C29/42 ; G11C29/50 ; G11C29/04

Abstract:
Techniques are presented for using erase stress and variations in the loop count (number of cycles) for various fail modes in non-volatile memories, including erase disturb and shallow erase. For detection of shallow erase, cells are programmed and then erased, where the variation (delta) in the number of erase loop counts can be used to determine defective blocks. To determine blocks prone to erase disturb, an erase stress is applied to unselected blocks, after which they are programmed: after then erasing one block, the next block can then be read to determine whether it has suffered erase disturb.
Public/Granted literature
- US20160125956A1 Erase Stress and Delta Erase Loop Count Methods for Various Fail Modes in Non-Volatile Memory Public/Granted day:2016-05-05
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