Invention Grant
- Patent Title: Internal spacers for nanowire transistors and method of fabrication thereof
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Application No.: US15335269Application Date: 2016-10-26
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Publication No.: US09935205B2Publication Date: 2018-04-03
- Inventor: Seiyon Kim , Daniel A. Simon , Nadia M. Rahhal-Orabi , Chul-Hyun Lim , Kelin J. Kuhn
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Green, Howard & Mughal LLP
- Main IPC: H01L29/775
- IPC: H01L29/775 ; H01L29/786 ; H01L27/088 ; H01L29/06 ; H01L21/02 ; H01L29/66 ; H01L29/161 ; H01L29/423 ; H01L29/78 ; H01L21/8238 ; B82Y10/00 ; H01L27/092 ; H01L29/165
Abstract:
A nanowire transistor of the present description may be produced with internal spacers formed by using sacrificial spacers during the fabrication thereof. Once the nanowire transistor is formed, the sacrificial spacers, which are position between the transistor gate and the source and drains (respectively), may be removed. The sacrificial material between channel nanowires of the nanowire transistor may then be removed and a dielectric material may be deposited to fill the spaces between the channel nanowires. The dielectric material not between the channel nanowires may be removed to form the internal spacers. External spacers, which are position between the transistor gate and the source and drains (respectively), may then be formed adjacent the internal spacers and transistor channel nanowires.
Public/Granted literature
- US20170047452A1 INTERNAL SPACERS FOR NANOWIRE TRANSISTORS AND METHOD OF FABRICATION THEREOF Public/Granted day:2017-02-16
Information query
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