公开(公告)号：US11887891B2

公开(公告)日：2024-01-30

申请号：US18098029

申请日：2023-01-17

申请人： Intel Corporation

发明人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

IPC分类号： H01L21/768 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L21/283 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528 ,  H01L29/08 ,  H01L29/423 ,  H01L29/16 ,  H01L29/45 ,  H01L21/285 ,  H01L23/535

CPC分类号： H01L21/76897 ,  H01L21/283 ,  H01L21/28123 ,  H01L21/28229 ,  H01L21/28255 ,  H01L21/28562 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/5226 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/785 ,  H01L29/495 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

摘要： A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

公开(公告)号：US10461082B2

公开(公告)日：2019-10-29

申请号：US15577734

申请日：2015-06-26

申请人： Intel Corporation

发明人： Willy Rachmady ,  Matthew V. Metz ,  Gilbert Dewey ,  Chandra S. Mohapatra ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Nadia M. Rahhal-Orabi ,  Tahir Ghani

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L21/8258 ,  H01L29/10

摘要： Non-silicon fin structures extend from a crystalline heteroepitaxial well material in a well recess of a substrate. III-V finFETs may be formed on the fin structures within the well recess while group IV finFETs are formed in a region of the substrate adjacent to the well recess. The well material may be electrically isolated from the substrate by an amorphous isolation material surrounding pillars passing through the isolation material that couple the well material to a seeding surface of the substrate and trap crystal growth defects. The pillars may be expanded over the well-isolation material by lateral epitaxial overgrowth, and the well recess filled with a single crystal of high quality. Well material may be planarized with adjacent substrate regions. N-type fin structures may be fabricated from the well material in succession with p-type fin structures fabricated from the substrate, or second epitaxial well.

公开(公告)号：US10930557B2

公开(公告)日：2021-02-23

申请号：US16819590

申请日：2020-03-16

申请人： Intel Corporation

发明人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

IPC分类号： H01L21/768 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L21/283 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528 ,  H01L29/08 ,  H01L29/423 ,  H01L29/16 ,  H01L29/45 ,  H01L21/285 ,  H01L23/535

摘要： A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

公开(公告)号：US10141226B2

公开(公告)日：2018-11-27

申请号：US15827491

申请日：2017-11-30

申请人： INTEL CORPORATION

发明人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

IPC分类号： H01L21/768 ,  H01L21/28 ,  H01L21/285 ,  H01L23/535 ,  H01L29/45 ,  H01L29/16 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L21/311 ,  H01L29/08 ,  H01L21/283 ,  H01L23/522 ,  H01L23/528 ,  H01L29/78 ,  H01L29/49

摘要： A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

公开(公告)号：US11600524B2

公开(公告)日：2023-03-07

申请号：US17147423

申请日：2021-01-12

申请人： Intel Corporation

发明人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

IPC分类号： H01L21/768 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L21/283 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528 ,  H01L29/08 ,  H01L29/423 ,  H01L29/16 ,  H01L29/45 ,  H01L21/285 ,  H01L23/535

摘要： A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

公开(公告)号：US10797150B2

公开(公告)日：2020-10-06

申请号：US15770468

申请日：2015-12-17

申请人： Intel Corporation

发明人： Sean T. Ma ,  Willy Rachmady ,  Matthew V. Metz ,  Chandra S. Mohapatra ,  Gilbert Dewey ,  Nadia M. Rahhal-Orabi ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Tahir Ghani

IPC分类号： H01L29/00 ,  H01L29/49 ,  H01L29/78 ,  H01L29/10 ,  H01L21/28 ,  H01L29/205 ,  H01L29/66

摘要： An apparatus including a non-planar body on a substrate, the body including a channel on a blocking material, and a gate stack on the body, the gate stack including a first gate electrode material including a first work function disposed on the channel material and a second gate electrode material including a second work function different from the first work function disposed on the channel material and on the blocking material. A method including forming a non-planar body on a substrate, the non-planar body including a channel on a blocking material, and forming a gate stack on the body, the gate stack including a first gate electrode material including a first work function disposed on the channel and a second gate electrode material including a second work function different from the first work function disposed on the channel and on the blocking material.

公开(公告)号：US11631737B2

公开(公告)日：2023-04-18

申请号：US15529481

申请日：2014-12-24

申请人： Intel Corporation

发明人： Sanaz K. Gardner ,  Willy Rachmady ,  Matthew V. Metz ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Chandra S. Mohapatra ,  Anand S. Murthy ,  Nadia M. Rahhal-Orabi ,  Nancy M. Zelick ,  Tahir Ghani

IPC分类号： H01L29/205 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L29/267 ,  H01L29/423 ,  H01L29/786 ,  H01L29/10 ,  H01L29/04

摘要： Embodiments of the invention include nanowire and nanoribbon transistors and methods of forming such transistors. According to an embodiment, a method for forming a microelectronic device may include forming a multi-layer stack within a trench formed in a shallow trench isolation (STI) layer. The multi-layer stack may comprise at least a channel layer, a release layer formed below the channel layer, and a buffer layer formed below the channel layer. The STI layer may be recessed so that a top surface of the STI layer is below a top surface of the release layer. The exposed release layer from below the channel layer by selectively etching away the release layer relative to the channel layer.

公开(公告)号：US11205707B2

公开(公告)日：2021-12-21

申请号：US15525571

申请日：2014-12-22

申请人： INTEL CORPORATION

发明人： Nadia M. Rahhal-Orabi ,  Tahir Ghani ,  Willy Rachmady ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Gilbert Dewey ,  Anand S. Murthy ,  Chandra S. Mohapatra

IPC分类号： H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L29/78

摘要： Systems and methods of optimizing a gate profile for performance and gate fill are disclosed. A semiconductor device having an optimized gate profile includes a semiconductor substrate and a fin extending above the semiconductor substrate. A pair of source and drain regions are disposed on opposite sides of a channel region. A gate stack is disposed over the channel region, where the gate stack includes a top portion separated from a bottom portion by a tapered portion. The top portion and at least a portion of the tapered portion are disposed above the fin.

公开(公告)号：US10431690B2

公开(公告)日：2019-10-01

申请号：US15575111

申请日：2015-06-26

申请人： Intel Corporation

发明人： Willy Rachmady ,  Matthew V. Metz ,  Gilbert Dewey ,  Chandra S. Mohapatra ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Sanaz K. Gardner

IPC分类号： H01L29/786 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

摘要： Crystalline heterostructures including an elevated fin structure extending from a sub-fin structure over a substrate. Devices, such as III-V transistors, may be formed on the raised fin structures while silicon-based devices (e.g., transistors) may be formed in other regions of the silicon substrate. A sub-fin isolation material localized to a transistor channel region of the fin structure may reduce source-to-drain leakage through the sub-fin, improving electrical isolation between source and drain ends of the fin structure. Subsequent to heteroepitaxially forming the fin structure, a portion of the sub-fin may be laterally etched to undercut the fin. The undercut is backfilled with sub-fin isolation material. A gate stack is formed over the fin. Formation of the sub-fin isolation material may be integrated into a self-aligned gate stack replacement process.

公开(公告)号：US20180096891A1

公开(公告)日：2018-04-05

申请号：US15827491

申请日：2017-11-30

申请人： INTEL CORPORATION

发明人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

IPC分类号： H01L21/768 ,  H01L29/423 ,  H01L21/28 ,  H01L21/283 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L29/45 ,  H01L29/16 ,  H01L29/08 ,  H01L23/535 ,  H01L23/528 ,  H01L23/522 ,  H01L21/311 ,  H01L21/285

CPC分类号： H01L21/76897 ,  H01L21/28123 ,  H01L21/28229 ,  H01L21/28255 ,  H01L21/283 ,  H01L21/28562 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

摘要： A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.