公开(公告)号：US11594448B2

公开(公告)日：2023-02-28

申请号：US16435259

申请日：2019-06-07

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Chul-Hyun Lim ,  Paul A. Nyhus ,  Elliot N. Tan ,  Charles H. Wallace

IPC: H01L21/768 ,  H01L21/311 ,  H01L29/423 ,  H01L29/417

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such semiconductor devices. In an embodiment, a method of fabricating a semiconductor device comprises, forming a first grating of parallel first lines, forming a second grating of parallel second lines, wherein the second lines are substantially orthogonal to the first lines, and wherein the first lines and second lines define a plurality of first openings, disposing a conformal mask layer over the first lines and the second lines, wherein the conformal mask layer partially fills the first openings and defines a second opening within each of the first openings, disposing a hardmask over the conformal mask layer, wherein the hardmask fills the second openings, patterning third openings into the hardmask, wherein the third openings clear the hardmask from at least one of the second openings, and removing the mask layer proximate to cleared second openings to clear first openings.

公开(公告)号：US09935205B2

公开(公告)日：2018-04-03

申请号：US15335269

申请日：2016-10-26

Applicant: INTEL CORPORATION

Inventor： Seiyon Kim ,  Daniel A. Simon ,  Nadia M. Rahhal-Orabi ,  Chul-Hyun Lim ,  Kelin J. Kuhn

IPC: H01L29/775 ,  H01L29/786 ,  H01L27/088 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L29/161 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8238 ,  B82Y10/00 ,  H01L27/092 ,  H01L29/165

CPC classification number: H01L29/78696 ,  B82Y10/00 ,  H01L21/02603 ,  H01L21/823807 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78651 ,  H01L29/78684

Abstract: A nanowire transistor of the present description may be produced with internal spacers formed by using sacrificial spacers during the fabrication thereof. Once the nanowire transistor is formed, the sacrificial spacers, which are position between the transistor gate and the source and drains (respectively), may be removed. The sacrificial material between channel nanowires of the nanowire transistor may then be removed and a dielectric material may be deposited to fill the spaces between the channel nanowires. The dielectric material not between the channel nanowires may be removed to form the internal spacers. External spacers, which are position between the transistor gate and the source and drains (respectively), may then be formed adjacent the internal spacers and transistor channel nanowires.

公开(公告)号：US20170047452A1

公开(公告)日：2017-02-16

申请号：US15335269

申请日：2016-10-26

Applicant: INTEL CORPORATION

Inventor： Seiyon Kim ,  Daniel A. Simon ,  Nadia M. Rahhal-Orabi ,  Chul-Hyun Lim ,  Kelin J. Kuhn

IPC: H01L29/786 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/78696 ,  B82Y10/00 ,  H01L21/02603 ,  H01L21/823807 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78651 ,  H01L29/78684

Abstract: A nanowire transistor of the present description may be produced with internal spacers formed by using sacrificial spacers during the fabrication thereof. Once the nanowire transistor is formed, the sacrificial spacers, which are position between the transistor gate and the source and drains (respectively), may be removed. The sacrificial material between channel nanowires of the nanowire transistor may then be removed and a dielectric material may be deposited to fill the spaces between the channel nanowires. The dielectric material not between the channel nanowires may be removed to form the internal spacers. External spacers, which are position between the transistor gate and the source and drains (respectively), may then be formed adjacent the internal spacers and transistor channel nanowires.

Abstract translation: 本描述的纳米线晶体管可以在其制造期间使用牺牲间隔物形成的内部间隔物来制造。 一旦形成了纳米线晶体管，就可以去除位于晶体管栅极和源极之间的排列（分别）的牺牲间隔物。 然后可以去除纳米线晶体管的沟道纳米线之间的牺牲材料，并且可以沉积介电材料以填充沟道纳米线之间的空间。 可以除去不在通道纳米线之间的电介质材料以形成内部间隔物。 位于晶体管栅极和源极之间的位置（分别）的外部间隔物可以随后形成在内部间隔物和晶体管沟道纳米线附近。

公开(公告)号：US09508796B2

公开(公告)日：2016-11-29

申请号：US14916093

申请日：2013-10-03

Applicant: INTEL CORPORATION

Inventor： Seiyon Kim ,  Daniel A. Simon ,  Nadia M. Rahhal-Orabi ,  Chul-Hyun Lim ,  Kelin J. Kuhn

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/161 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  H01L29/78

CPC classification number: H01L29/78696 ,  B82Y10/00 ,  H01L21/02603 ,  H01L21/823807 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78651 ,  H01L29/78684

Abstract: A nanowire transistor of the present description may be produced with internal spacers formed by using sacrificial spacers during the fabrication thereof. Once the nanowire transistor is formed, the sacrificial spacers, which are position between the transistor gate and the source and drains (respectively), may be removed. The sacrificial material between channel nanowires of the nanowire transistor may then be removed and a dielectric material may be deposited to fill the spaces between the channel nanowires. The dielectric material not between the channel nanowires may be removed to form the internal spacers. External spacers, which are position between the transistor gate and the source and drains (respectively), may then be formed adjacent the internal spacers and transistor channel nanowires.

Abstract translation: 本描述的纳米线晶体管可以在其制造期间使用牺牲间隔物形成的内部间隔物来制造。 一旦形成了纳米线晶体管，就可以去除位于晶体管栅极和源极之间的排列（分别）的牺牲间隔物。 然后可以去除纳米线晶体管的沟道纳米线之间的牺牲材料，并且可以沉积介电材料以填充沟道纳米线之间的空间。 可以除去不在通道纳米线之间的电介质材料以形成内部间隔物。 位于晶体管栅极和源极之间的位置（分别）的外部间隔物可以随后形成在内部间隔物和晶体管沟道纳米线附近。