Invention Application
WO2017142849A1 SEMICONDUCTOR ON INSULATOR STRUCTURE COMPRISING A BURIED HIGH RESISTIVITY LAYER
审中-公开
半导体绝缘体结构包括一个埋地高电阻率层
- Patent Title: SEMICONDUCTOR ON INSULATOR STRUCTURE COMPRISING A BURIED HIGH RESISTIVITY LAYER
- Patent Title (中): 半导体绝缘体结构包括一个埋地高电阻率层
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Application No.: PCT/US2017/017756Application Date: 2017-02-14
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Publication No.: WO2017142849A1Publication Date: 2017-08-24
- Inventor: PEIDOUS, Igor , JONES, Andrew M. , KOMMU, Srikanth , MENDEZ, Horacio Josue
- Applicant: SUNEDISON SEMICONDUCTOR LIMITED
- Applicant Address: 9 Battery Road #15-01, Straits Trading Building Singapore 049910 SG
- Assignee: SUNEDISON SEMICONDUCTOR LIMITED
- Current Assignee: SUNEDISON SEMICONDUCTOR LIMITED
- Current Assignee Address: 9 Battery Road #15-01, Straits Trading Building Singapore 049910 SG
- Agency: SCHUTH, Richard A. et al.
- Priority: US62/297,252 20160219
- Main IPC: H01L21/20
- IPC: H01L21/20 ; H01L21/762 ; H01L27/12
Abstract:
A cost effective process flow for manufacturing semiconductor on insulator structures is parallel is provided. Each of the multiple semiconductor-on-insulator composite structures prepared in parallel comprises a charge trapping layer (CTL).
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