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    HIGH RESISTIVITY SILICON-ON-INSULATOR WAFER MANUFACTURING METHOD FOR REDUCING SUBSTRATE LOSS
    5.
    发明申请
    HIGH RESISTIVITY SILICON-ON-INSULATOR WAFER MANUFACTURING METHOD FOR REDUCING SUBSTRATE LOSS 审中-公开
    用于减少基板损耗的高电阻率硅绝缘体制造方法

    公开(公告)号：WO2016036317A1

    公开(公告)日：2016-03-10

    申请号：PCT/SG2015/050299

    申请日：2015-09-04

    Applicant: SUNEDISON SEMICONDUCTOR LIMITED

    Inventor： LIU, Qingmin ,  WANG, Gang

    IPC: H01L21/762

    CPC classification number: H01L29/66833 ,  H01L21/02381 ,  H01L21/02428 ,  H01L21/0254 ,  H01L21/02598 ,  H01L21/304 ,  H01L21/324 ,  H01L21/76254 ,  H01L21/763 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4234 ,  H01L29/517 ,  H01L29/518 ,  H01L29/792

    Abstract: A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm; a semiconductor nitride layer in contact with the semiconductor handle substrate, the semiconductor nitride layer selected from the group consisting of aluminum nitride, boron nitride, indium nitride, gallium nitride, aluminum gallium nitride, aluminum gallium indium nitride, aluminum gallium indium boron nitride, and combinations thereof; a dielectric layer in contact with the semiconductor nitride layer; and a semiconductor device layer in contact with the dielectric layer.

    Abstract translation: 提供了一种多层复合结构体及其制备方法。 多层复合结构包括具有至少约500欧姆 - 厘米的最小体积电阻率的半导体处理衬底; 与半导体处理衬底接触的半导体氮化物层，选自氮化铝，氮化硼，氮化铟，氮化镓，氮化镓铝，氮化镓铟氮化镓，铝镓铟氮化硼的氮化物半导体层和 其组合; 与所述半导体氮化物层接触的电介质层; 以及与电介质层接触的半导体器件层。

    HIGH RESISTIVITY SOI WAFERS AND A METHOD OF MANUFACTURING THEREOF
    6.
    发明申请
    HIGH RESISTIVITY SOI WAFERS AND A METHOD OF MANUFACTURING THEREOF 审中-公开
    高电阻SOI波形及其制造方法

    公开(公告)号：WO2015112308A1

    公开(公告)日：2015-07-30

    申请号：PCT/US2014/072546

    申请日：2014-12-29

    Applicant: SUNEDISON SEMICONDUCTOR LIMITED ,  PEIDOUS, Igor

    Inventor： PEIDOUS, Igor ,  KOMMU, Srikanth ,  WANG, Gang ,  THOMAS, Shawn G.

    IPC: H01L21/762

    CPC classification number: H01L21/76251 ,  H01L21/76254

    Abstract: A high resistivity single crystal semiconductor handle structure for use in the manufacture of SOI structure is provided. The handle structure comprises an intermediate semiconductor layer between the handle substrate and the buried oxide layer. The intermediate semiconductor layer comprises a polycrystalline, amorphous, nanocrystalline, or monocrystalline structure and comprises a material selected from the group consisting of Si 1-x Ge x , Si 1-x C x , Si 1-x-y Ge x Sn y , Si 1-x-y-z Ge x Sn y C z , Ge 1-x Sn x , group IIIA-nitrides, semiconductor oxides, and any combination thereof.

    Abstract translation: 提供了用于制造SOI结构的高电阻率单晶半导体手柄结构。 手柄结构包括在处理衬底和掩埋氧化物层之间的中间半导体层。 中间半导体层包括多晶，非晶，纳米晶体或单晶结构，并且包括选自Si1-xGex，Si1-xCx，Si1-x-yGexSny，Si1-xy-zGexSnyCz，Ge1-xSnx， IIIA-氮化物，半导体氧化物及其任何组合。

    A METHOD OF MANUFACTURING SILICON GERMANIUM-ON-INSULATOR
    9.
    发明申请
    A METHOD OF MANUFACTURING SILICON GERMANIUM-ON-INSULATOR 审中-公开
    一种制造硅绝缘体的方法

    公开(公告)号：WO2016196011A1

    公开(公告)日：2016-12-08

    申请号：PCT/US2016/033097

    申请日：2016-05-18

    Applicant: SUNEDISON SEMICONDUCTOR LIMITED ,  THOMAS, Shawn G.

    Inventor： THOMAS, Shawn G. ,  WANG, Gang

    IPC: H01L21/762 ,  H01L21/02

    CPC classification number: H01L21/76251 ,  H01L21/0242 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/3065

    Abstract: The disclosed method is suitable for producing a SiGe-on-insulator structure. According to some embodiments of the method, a layer comprising SiGe is deposited on silicon-on-insulator substrate comprising an ultra-thin silicon top layer. In some embodiments, the layer comprising SiGe is deposited by epitaxial deposition. In some embodiments, the SiGe epitaxial layer is high quality since it is produced by engineering the strain relaxation at the Si/buried oxide interface. In some embodiments, the method accomplishes elastic strain relaxation of SiGe grown on a few monolayer thick Si layer that is weakly bonded to the underline oxide.

    Abstract translation: 所公开的方法适用于制造绝缘体上的SiGe结构。 根据该方法的一些实施例，包括SiGe的层被沉积在包括超薄硅顶层的绝缘体上的衬底上。 在一些实施例中，通过外延沉积沉积包含SiGe的层。 在一些实施例中，SiGe外延层是高质量的，因为其通过在Si /掩埋氧化物界面处工程化应变松弛而产生。 在一些实施方案中，该方法实现了在与下划线氧化物弱结合的少量单层厚Si层上生长的SiGe的弹性应变弛豫。

    THERMALLY STABLE CHARGE TRAPPING LAYER FOR USE IN MANUFACTURE OF SEMICONDUCTOR-ON-INSULATOR STRUCTURES
    10.
    发明申请
    THERMALLY STABLE CHARGE TRAPPING LAYER FOR USE IN MANUFACTURE OF SEMICONDUCTOR-ON-INSULATOR STRUCTURES 审中-公开
    用于制造半导体绝缘体结构的热稳定电荷捕获层

    公开(公告)号：WO2016149113A1

    公开(公告)日：2016-09-22

    申请号：PCT/US2016/022089

    申请日：2016-03-11

    Applicant: SUNEDISON SEMICONDUCTOR LIMITED ,  USENKO, Alex

    Inventor： USENKO, Alex

    IPC: H01L21/762

    CPC classification number: H01L21/7627 ,  H01L21/0203 ,  H01L21/02238 ,  H01L21/02258 ,  H01L21/76254 ,  H01L21/76286 ,  H01L27/1203

    Abstract: A single crystal semiconductor handle substrate for use in the manufacture of semiconductor-on-insulator (e.g., silicon-on-insulator (SOI)) structure is etched to form a porous layer in the front surface region of the wafer. The etched region is oxidized and then filled with a semiconductor material, which may be polycrystalline or amorphous. The surface is polished to render it bondable to a semiconductor donor substrate. Layer transfer is performed over the polished surface thus creating semiconductor-on-insulator (e.g., silicon-on-insulator (SOI)) structure having 4 layers: the handle substrate, the composite layer comprising filled pores, a dielectric layer (e.g., buried oxide), and a device layer. The structure can be used as initial substrate in fabricating radiofrequency chips. The resulting chips have suppressed parasitic effects, particularly, no induced conductive channel below the buried oxide.

    Abstract translation: 蚀刻用于制造绝缘体上半导体（例如，绝缘体上硅（SOI））结构的单晶半导体处理衬底，以在晶片的前表面区域中形成多孔层。 蚀刻区域被氧化，然后用半导体材料填充，半导体材料可以是多晶的或非晶的。 该表面被抛光以使其能够与半导体供体基板结合。 在抛光表面上进行层转移，从而产生绝缘体上半导体（例如，绝缘体上硅（SOI））结构，其具有4层：手柄衬底，复合层包括填充孔，电介质层 氧化物）和器件层。 该结构可用作制造射频芯片的初始衬底。 所得到的芯片抑制了寄生效应，特别是在掩埋氧化物之下没有诱导的导电通道。

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