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    HIGH RESISTIVITY SOI WAFERS AND A METHOD OF MANUFACTURING THEREOF
    6.
    发明申请
    HIGH RESISTIVITY SOI WAFERS AND A METHOD OF MANUFACTURING THEREOF 审中-公开
    高电阻SOI波形及其制造方法

    公开(公告)号：WO2015112308A1

    公开(公告)日：2015-07-30

    申请号：PCT/US2014/072546

    申请日：2014-12-29

    Applicant: SUNEDISON SEMICONDUCTOR LIMITED ,  PEIDOUS, Igor

    Inventor： PEIDOUS, Igor ,  KOMMU, Srikanth ,  WANG, Gang ,  THOMAS, Shawn G.

    IPC: H01L21/762

    CPC classification number: H01L21/76251 ,  H01L21/76254

    Abstract: A high resistivity single crystal semiconductor handle structure for use in the manufacture of SOI structure is provided. The handle structure comprises an intermediate semiconductor layer between the handle substrate and the buried oxide layer. The intermediate semiconductor layer comprises a polycrystalline, amorphous, nanocrystalline, or monocrystalline structure and comprises a material selected from the group consisting of Si 1-x Ge x , Si 1-x C x , Si 1-x-y Ge x Sn y , Si 1-x-y-z Ge x Sn y C z , Ge 1-x Sn x , group IIIA-nitrides, semiconductor oxides, and any combination thereof.

    Abstract translation: 提供了用于制造SOI结构的高电阻率单晶半导体手柄结构。 手柄结构包括在处理衬底和掩埋氧化物层之间的中间半导体层。 中间半导体层包括多晶，非晶，纳米晶体或单晶结构，并且包括选自Si1-xGex，Si1-xCx，Si1-x-yGexSny，Si1-xy-zGexSnyCz，Ge1-xSnx， IIIA-氮化物，半导体氧化物及其任何组合。

    HIGH RESISTIVITY SILICON-ON-INSULATOR SUBSTRATE COMPRISING A CHARGE TRAPPING LAYER FORMED ON A SUBSTRATE WITH A ROUGH SURFACE
    8.
    发明申请
    HIGH RESISTIVITY SILICON-ON-INSULATOR SUBSTRATE COMPRISING A CHARGE TRAPPING LAYER FORMED ON A SUBSTRATE WITH A ROUGH SURFACE 审中-公开
    包含在具有粗糙表面的衬底上形成的电荷陷阱层的高电阻率绝缘体上硅衬底

    公开(公告)号：WO2017142704A1

    公开(公告)日：2017-08-24

    申请号：PCT/US2017/015813

    申请日：2017-01-31

    Applicant: SUNEDISON SEMICONDUCTOR LIMITED ,  PEIDOUS, Igor

    Inventor： PEIDOUS, Igor ,  JONES, Andrew M. ,  KOMMU, Srikanth ,  WANG, Gang ,  LIBBERT, Jeffrey L.

    IPC: H01L21/762 ,  H01L21/28

    CPC classification number: H01L21/76254

    Abstract: A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and the front surface of the single crystal semiconductor handle substrate has a surface roughness of at least about 0.1 micrometers as measured according to the root mean square method over a surface area of at least 30 micrometers by 30 micrometers. The composite structure further comprises a charge trapping layer in contact with the front surface, the charge trapping layer comprising poly crystalline silicon, the poly crystalline silicon comprising grains having a plurality of crystal orientations; a dielectric layer in contact with the charge trapping layer; and a single crystal semiconductor device layer in contact with the dielectric layer.

    Abstract translation: 提供了多层复合结构和制备多层复合结构的方法。 多层复合结构包括具有至少约500ohm-cm的最小体区电阻率的半导体处理衬底，并且单晶半导体处理衬底的前表面具有根据根部测量的至少约0.1微米的表面粗糙度 均方法在至少30微米×30微米的表面积上。 所述复合结构还包括与所述前表面接触的电荷俘获层，所述电荷俘获层包含多晶硅，所述多晶硅包含具有多个晶体取向的晶粒; 与电荷俘获层接触的介电层; 以及与介电层接触的单晶半导体器件层。

    A SYSTEM-ON-CHIP ON A SEMICONDUCTOR-ON-INSULATOR WAFER AND A METHOD OF MANUFACTURING
    9.
    发明申请
    A SYSTEM-ON-CHIP ON A SEMICONDUCTOR-ON-INSULATOR WAFER AND A METHOD OF MANUFACTURING 审中-公开
    半导体绝缘体波导上的系统芯片及其制造方法

    公开(公告)号：WO2016081363A1

    公开(公告)日：2016-05-26

    申请号：PCT/US2015/060871

    申请日：2015-11-16

    Applicant: SUNEDISON SEMICONDUCTOR LIMITED ,  KOMMU, Srikanth

    Inventor： KOMMU, Srikanth ,  MENDEZ, Horacio Josue ,  PEIDOUS, Igor

    IPC: H01L27/12 ,  H01L21/762 ,  H01L27/06

    CPC classification number: H01L27/1203 ,  H01L21/76254 ,  H01L21/763 ,  H01L27/0688

    Abstract: A method of preparing a semiconductor-on-insulator (e.g., silicon-on-insulator) structure, and more particularly a method for producing an integrated circuit device on a semiconductor-on-insulator structure is provided. The method comprises forming multiple integrated circuit device types on a semiconductor-on-insulator structure in different regions of the device layer. The integrate circuit device types include a module of radiofrequency devices and a module of CMOS devices.

    Abstract translation: 提供一种制备绝缘体上半导体（例如，绝缘体上硅）结构的方法，更具体地说，提供了一种在绝缘体上半导体结构上制造集成电路器件的方法。 该方法包括在器件层的不同区域中的绝缘体上半导体结构上形成多个集成电路器件类型。 集成电路设备类型包括射频设备的模块和CMOS设备的模块。

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