公开(公告)号：WO2023044237A1

公开(公告)日：2023-03-23

申请号：PCT/US2022/075574

申请日：2022-08-29

Applicant: GLOBALWAFERS CO., LTD.

Inventor： ZEPEDA, Salvador ,  LUTER, William ,  PHILLIPS, Richard Joseph

IPC: C30B15/02 ,  C30B29/06 ,  C30B15/00 ,  C04B35/14

Abstract: Crystal pulling systems having composite polycrystalline silicon feed tubes, methods for forming such tubes, and methods for forming a single crystal silicon ingot with use of such tubes. The composite polycrystalline silicon feed tubes include quartz and at least one dopant. The composite polycrystalline silicon feed tube may be made by a slip cast method.

公开(公告)号：WO2022271561A1

公开(公告)日：2022-12-29

申请号：PCT/US2022/034034

申请日：2022-06-17

Applicant: GLOBALWAFERS CO., LTD.

Inventor： LIN, Shan-Hui ,  TU, Chun-Chin ,  CHEN, Chi-Yung ,  TSAI, Feng-Chien ,  HUANG, Hong-Huei ,  LU, Zheng

IPC: C30B15/20 ,  C30B29/06 ,  C30B15/00 ,  C30B25/16 ,  C30B25/20 ,  G01N2021/8461

Abstract: Methods for determining suitability of Czochralski growth conditions to produce silicon substrates for epitaxy. The methods involve evaluating substrates sliced from ingots grown under different growth conditions (e.g., impurity profiles) by imaging the wafer by infrared depolarization. An infrared depolarization parameter is generated for each epitaxial wafer. The parameters may be compared to determine which growth conditions are well-suited to produce substrates for epitaxial and/or post-epi heat treatments.

公开(公告)号：WO2022240726A1

公开(公告)日：2022-11-17

申请号：PCT/US2022/028285

申请日：2022-05-09

Applicant: GLOBALWAFERS CO., LTD.

Inventor： WANG, Gang

IPC: H01L21/3065 ,  H01L21/3213 ,  C23C16/02 ,  C23C16/24 ,  C23C16/56 ,  C23C16/0236 ,  H01L21/32137

Abstract: Methods for etching a semiconductor structure and for conditioning a processing reactor in which a single semiconductor structure is treated are disclosed. An engineered polycrystalline silicon surface layer is deposited on a susceptor which supports the semiconductor structure. The polycrystalline silicon surface layer may be engineered by controlling the temperature at which the layer is deposited, by grooving the polycrystalline silicon surface layer or by controlling the thickness of the polycrystalline silicon surface layer.

公开(公告)号：WO2022182534A1

公开(公告)日：2022-09-01

申请号：PCT/US2022/016188

申请日：2022-02-11

Applicant: GLOBALWAFERS CO., LTD.

Inventor： JI, JunHwan ,  YUN, WooJin ,  MEYER, Benjamin Michael ,  HUDSON, Carissima Marie ,  RYU, JaeWoo

IPC: C30B15/00 ,  C30B29/06

Abstract: Ingot puller apparatus having a compound exhaust tube and methods for selecting the length of the lower and upper portions of the compound exhaust tube are disclosed. In some embodiments, the upper portion of the compound exhaust tube is made of graphite and the lower portion is made of stainless steel.

公开(公告)号：WO2021050176A1

公开(公告)日：2021-03-18

申请号：PCT/US2020/044844

申请日：2020-08-04

Applicant: GLOBALWAFERS CO., LTD.

Inventor： RYU, JaeWoo ,  HUDSON, Carissima Marie

IPC: C30B15/00 ,  C30B15/04 ,  C30B15/20 ,  C30B15/22 ,  C30B29/06

Abstract: A method for growing a single crystal silicon ingot by the continuous Czochralski method is disclosed. The melt depth and thermal conditions are constant during growth because the silicon melt is continuously replenished as it is consumed, and the crucible location is fixed. The critical v/G is determined by the hot zone configuration, and the continuous replenishment of silicon to the melt during growth enables growth of the ingot at a constant pull rate consistent with the critical v/G during growth of a substantial portion of the main body of the ingot. The continuous replenishment of silicon is accompanied by periodic or continuous nitrogen addition to the melt to result in a nitrogen doped ingot.

公开(公告)号：WO2018035016A1

公开(公告)日：2018-02-22

申请号：PCT/US2017/046710

申请日：2017-08-14

Applicant: MALLINCKRODT NUCLEAR MEDICINE LLC

Inventor： BARBOSA, Luis Antonio M.M. ,  DEKKER, Frits ,  GERRITSEN, Marjolijn ,  HERMELER, Mark

IPC: C01G39/00 ,  G21G1/00

CPC classification number: G21G1/001 ,  B01D15/363 ,  B01D15/426 ,  C01G39/003 ,  G21G2001/0036

Abstract: Methods for purifying the molybdenum-99 isotope are disclosed. Molybdenum-99 is loaded onto an anion exchange column and extracted. In some embodiments, the extraction solution may include nitric acid and nitrate salts. In other embodiments, a two stage elution is performed in which a nitic acid containing eluent and a hydroxide containing eluent are used in succession to extract molybdenum-99.

Abstract translation: 公开了纯化钼-99同位素的方法。 将钼-99装载到阴离子交换柱上并提取。 在一些实施方案中，提取溶液可以包含硝酸盐和硝酸盐。 在其他实施方案中，进行两阶段洗脱，其中连续使用含硝酸的洗脱剂和含氢氧化物的洗脱剂来提取钼-99。

公开(公告)号：WO2017155808A1

公开(公告)日：2017-09-14

申请号：PCT/US2017/020634

申请日：2017-03-03

Applicant: SUNEDISON SEMICONDUCTOR LIMITED

Inventor： KWESKIN, Sasha Joseph

IPC: H01L21/762 ,  H01L21/02

CPC classification number: H01L21/76254 ,  H01L21/0214 ,  H01L21/02274 ,  H01L21/0262 ,  H01L27/1203

Abstract: A method is provided for preparing a semiconductor-on-insulator structure comprising a silicon nitride layer deposited by plasma deposition.

Abstract translation: 提供了一种用于制备包括通过等离子体沉积沉积的氮化硅层的绝缘体上半导体结构的方法。

公开(公告)号：WO2017155805A1

公开(公告)日：2017-09-14

申请号：PCT/US2017/020619

申请日：2017-03-03

Applicant: SUNEDISON SEMICONDUCTOR LIMITED

Inventor： KWESKIN, Sasha Joseph

IPC: H01L21/762 ,  H01L21/20

Abstract: A method is provided for preparing a semiconductor-on-insulator structure comprising a flowable insulating layer or a reflowable insulating layer.

Abstract translation: 提供了一种用于制备包括可流动绝缘层或可回流绝缘层的绝缘体上半导体结构的方法。

公开(公告)号：WO2016196011A1

公开(公告)日：2016-12-08

申请号：PCT/US2016/033097

申请日：2016-05-18

Applicant: SUNEDISON SEMICONDUCTOR LIMITED ,  THOMAS, Shawn G.

Inventor： THOMAS, Shawn G. ,  WANG, Gang

IPC: H01L21/762 ,  H01L21/02

CPC classification number: H01L21/76251 ,  H01L21/0242 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/3065

Abstract: The disclosed method is suitable for producing a SiGe-on-insulator structure. According to some embodiments of the method, a layer comprising SiGe is deposited on silicon-on-insulator substrate comprising an ultra-thin silicon top layer. In some embodiments, the layer comprising SiGe is deposited by epitaxial deposition. In some embodiments, the SiGe epitaxial layer is high quality since it is produced by engineering the strain relaxation at the Si/buried oxide interface. In some embodiments, the method accomplishes elastic strain relaxation of SiGe grown on a few monolayer thick Si layer that is weakly bonded to the underline oxide.

Abstract translation: 所公开的方法适用于制造绝缘体上的SiGe结构。 根据该方法的一些实施例，包括SiGe的层被沉积在包括超薄硅顶层的绝缘体上的衬底上。 在一些实施例中，通过外延沉积沉积包含SiGe的层。 在一些实施例中，SiGe外延层是高质量的，因为其通过在Si /掩埋氧化物界面处工程化应变松弛而产生。 在一些实施方案中，该方法实现了在与下划线氧化物弱结合的少量单层厚Si层上生长的SiGe的弹性应变弛豫。

公开(公告)号：WO2016081356A1

公开(公告)日：2016-05-26

申请号：PCT/US2015/060854

申请日：2015-11-16

Applicant: SUNEDISON SEMICONDUCTOR LIMITED ,  PEIDOUS, Igor

Inventor： PEIDOUS, Igor ,  FEI, Lu ,  LIBBERT, Jeffrey Louis ,  JONES, Andrew M. ,  USENKO, Alex ,  WANG, Gang ,  THOMAS, Shawn G. ,  KOMMU, Srikanth

IPC: H01L21/762

CPC classification number: H01L21/76254

Abstract: A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.

Abstract translation: 提供了半导体绝缘体多层结构。 多层包括高电阻率单晶半导体处理衬底，包括硅，锗或硅锗的任选松弛的半导体层，可选的多晶硅层，电介质层和单晶半导体器件层。