公开(公告)号：EP0630115A3

公开(公告)日：1995-03-22

申请号：EP94303952.9

申请日：1994-06-01

申请人： PILKINGTON MICRO-ELECTRONICS LIMITED

发明人： Jones, Gareth James ,  Work, Gordon Stirling

IPC分类号： H03K19/177 ,  H03K19/173

CPC分类号： H03K19/17736 ,  H03K19/1736 ,  H03K19/17704 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/17796

摘要： A configurable semi-conductor integrated circuit comprising an area thereof formed with a plurality of logic circuits at discrete sites or cells (cc) respectively defining a matrix array of cells. The matrix array of cells is subdivided at least into zones comprising a porting arrangement for each zone and a hierarchical routing resource structure comprising:-
(i) global connection parts (G,X) having selectable connections with the porting arrangement of each zone, (ii) medium connection parts (M) extending from the porting arrangement and selectably connectable with at least some of the cells in a zone, and (iii) local direct connection paths comprising a restricted signal translation system. The application also describes a configurable semi-conductor integrated circuit comprising a matrix array of core cells (cc), each of the cells having a first simple function in common and at least one subsidiary function, there being at least two different subsidiary functions, the core cells being grouped in tiles comprising a matrix array of the core cells smaller than the whole array and wherein each tile has at least one of each different subsidiary functions and wherein the tiles of core cells are arranged so as to uniformly cover the array. Preferably there are fours cells to a tile and the preferred subsidiary function are:- wired-OR, XOR, D-type flip flop and latch function.

公开(公告)号：EP0560595A2

公开(公告)日：1993-09-15

申请号：EP93301830.1

申请日：1993-03-10

申请人： Pilkington Micro-Electronics Limited

发明人： Austin, Kenneth

IPC分类号： G06F15/80

CPC分类号： G06N3/04

摘要： The invention relates to an improved artificial digital neuron, an enhanced artificial neural network architecture together with a reduced training neural network training algorithm. The digital neuron comprises an n bit input one bit output device utilising a random access memory having 2" locations of one bit each. The neuron is programmed by the network training algorithm with the neuron fire state (on or off) in accordance with the synaptic weights allocated to the input code combination pattern for that neuron within the neural network. The digital neuron operates as a look-up table device deriving the neuron firing state, for each n bit digital code pattern applied to its input paths, from the random access memory location identified by the digital code pattern. The synaptic weights allocated to each digital code pattern for a particular neuron in the network cause the neuron to provide as an input correlation function or an interconnect function. The network architecture is based upon digital neurons providing either correlation or interconnection functions allowing a reduced interconnection arrangement where the output of each neuron in the input and hidden layers is connected only to an input path of a corresponding or immediately above or below neuron in the next layer. The training algorithm maps each pattern (as a function or interconnect) into neurons that lie on the path between a positive input (1) and the network output.

摘要翻译： 本发明涉及一种改进的人造数字神经元，一种增强的人工神经网络结构以及一种减少的训练神经网络训练算法。 数字神经元包括利用具有每个1位的2个位置的随机存取存储器的n位输入一位输出装置。 根据神经网络内神经元输入代码组合模式的突触权重，神经元由神经元激发状态（开启或关闭）通过网络训练算法进行编程。 数字神经元作为从由数字码型识别的随机存取存储器位置中，对应用于其输入路径的每个n位数字码模式，导出神经元发射状态的查找表装置。 分配给网络中特定神经元的每个数字代码模式的突触权重导致神经元提供作为输入相关函数或互连功能。 网络架构基于提供相关或互连功能的数字神经元，允许减少的互连布置，其中输入和隐藏层中的每个神经元的输出仅连接到下一个对应的或紧邻上方或下方的神经元的输入路径 层。 训练算法将每个模式（作为一个功能或互连）映射到位于正输入（1）和网络输出之间的路径上的神经元。

公开(公告)号：EP0536943A2

公开(公告)日：1993-04-14

申请号：EP92308939.5

申请日：1992-09-30

申请人： Pilkington Micro-Electronics Limited

发明人： Austin, Kenneth

IPC分类号： G06F12/14

CPC分类号： G06F21/75 ,  G11C7/24 ,  G11C16/22 ,  H04L9/0662 ,  H04L2209/125

摘要： A data security arrangement is provided to protect configuration data to be stored in static random access memories (38) in semiconductor programmable logic devices PLD. The configuration data, which is vulnerable to illegal duplication, is normally held in a read only memory ROM, typically an erasable programmable read only memory.
A data coding means is provided to code the configuration data to be loaded to the PLD and a data decoding means is provided in the PLD to decode the coded configuration data. The coding and decoding means each incorporate maximal length shift registers (12, 25) which generate a pseudo-random sequence of bits. A key value is input to the shift register (12) in the coding means forcing it to start at a particular point in the sequence. The output (bits B28 and B31) of this register is combined in an EXCLUSIVE-OR gate (20) with configuration data and coded data is written to the read only memory ROM (24). The decoding means in the PLD has a corresponding key value held in a non-volatile memory (28) in the PLD. This is applied to the register (25) of the decoding means whose output (bits B28 and B31) are combined in an EXCLUSIVE-OR GATE (34) with coded configuration data CDIC read from the ROM (24) to produce decoded configuration data CDOD to be sotred in the memories (38).

摘要翻译： 提供数据安全装置以保护要存储在半导体可编程逻辑器件PLD中的静态随机存取存储器（38）中的配置数据。 易于非法复制的配置数据通常被保存在只读存储器ROM中，通常是可擦除可编程只读存储器。 提供数据编码装置来编码要加载到PLD的配置数据，并且在PLD中提供数据解码装置以对编码的配置数据进行解码。 编码和解码装置每个都包含最大长度移位寄存器（12,25），其生成伪随机的比特序列。 键值被输入到编码装置中的移位寄存器（12），强制它在序列中的特定点开始。 该寄存器的输出（位B28和B31）在异或门（20）中与配置数据组合，编码数据被写入只读存储器ROM（24）。 PLD中的解码装置具有保存在PLD中的非易失性存储器（28）中的对应的键值。 这被应用于解码装置的寄存器（25），其解码装置的输出（比特B28和B31）与从ROM（24）读取的编码配置数据CDIC在独占或门（34）中组合以产生解码的配置数据CDOD 被记录在记忆中（38）。

公开(公告)号：EP0512536A2

公开(公告)日：1992-11-11

申请号：EP92107697.2

申请日：1992-05-07

申请人： KABUSHIKI KAISHA TOSHIBA ,  PILKINGTON MICRO-ELECTRONICS LIMITED

发明人： Saeki, Yukihiro, c/o Intellectual Property Div. ,  Muroga, Hiroki, c/o Intellectual Property Div. ,  Shigematsu, Tomohisa c/o Intellectual Property Div ,  Hibi, Toshio, c/o Intellectual Property Div. ,  Kawahara, Yasuo, c/o Intellectual Property Div. ,  Maru, Kazunao, c/o Intellectual Property Div. ,  Austin, Kenneth ,  Work, Gordon Stirling ,  Wedgwood, Darren Martin

IPC分类号： H03K19/177

CPC分类号： H03K19/17764 ,  G11C11/404 ,  G11C11/412 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1774

摘要： A programmable logic unit circuit comprising a data memory circuit (10), a combinational logic circuit (13) supplied with at least two input signals, two input select circuits (11,12) for, based on the stored data in the data memory circuit (10), selecting the two input signals supplied to the combinational logic circuit (13) from more than two input signals, a clock-synchronized circuit (14) for supplying the output signal from the combinational logic circuit (13) in synchronization with a clock signal, and a 3-state-output type output select circuit (16) for selecting either the output signal of the combinational logic circuit (13) or the output signal of the clock-synchronized circuit (14), depending on the stored data in the data memory circuit (10).

摘要翻译： 一种可编程逻辑单元电路，包括数据存储电路（10），提供有至少两个输入信号的组合逻辑电路（13），用于基于数据存储电路中存储的数据的两个输入选择电路（11,12） 从多于两个的输入信号中选择提供给组合逻辑电路的两个输入信号;时钟同步电路（14），用于与时钟信号同步地提供来自组合逻辑电路的输出信号， 输出型输出选择电路（16），用于根据数据存储电路中存储的数据选择组合逻辑电路的输出信号或时钟同步电路的输出信号。

公开(公告)号：EP0220816A3

公开(公告)日：1988-11-23

申请号：EP86306965

申请日：1986-09-10

申请人： Pilkington Micro-Electronics Limited

发明人： Austin, Kenneth

IPC分类号： H03K17/687

CPC分类号： H03K19/1778 ,  G06F17/5027 ,  H03K5/026 ,  H03K17/687 ,  H03K19/1733 ,  H03K19/1736 ,  H03K19/17704

摘要： A gated binary signal transmission circuit in a field effect semiconductor chip comprises a single signal-pass transistor (20A, B) connected between a bit signal input (28A, B) to one of its electrodes (24A, B) and a bit signal output (12A, B) from another of its electrodes (26A, B). Its control electrode (22A, B) is connected for temporary energisations by switching circuitry (32,34) operative only at prescribed intervals, the single signal-pass transistor (20A, B) being operative to pass signals between such energisations of its control electrode (22A, B). Conduction of the single signal-pass transistor between energisations will persist, though with some decay, due to inherent capacitance and the control electrode being left "floating" between energisations.

公开(公告)号：EP0512536A3

公开(公告)日：1995-08-02

申请号：EP92107697.2

申请日：1992-05-07

申请人： KABUSHIKI KAISHA TOSHIBA ,  PILKINGTON MICRO-ELECTRONICS LIMITED

发明人： Saeki, Yukihiro, c/o Intellectual Property Div. ,  Muroga, Hiroki, c/o Intellectual Property Div. ,  Shigematsu, Tomohisa c/o Intellectual Property Div ,  Hibi, Toshio, c/o Intellectual Property Div. ,  Kawahara, Yasuo, c/o Intellectual Property Div. ,  Maru, Kazunao, c/o Intellectual Property Div. ,  Austin, Kenneth ,  Work, Gordon Stirling ,  Wedgwood, Darren Martin

IPC分类号： H03K19/177

CPC分类号： H03K19/17764 ,  G11C11/404 ,  G11C11/412 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1774

摘要： A programmable logic unit circuit comprising a data memory circuit (10), a combinational logic circuit (13) supplied with at least two input signals, two input select circuits (11,12) for, based on the stored data in the data memory circuit (10), selecting the two input signals supplied to the combinational logic circuit (13) from more than two input signals, a clock-synchronized circuit (14) for supplying the output signal from the combinational logic circuit (13) in synchronization with a clock signal, and a 3-state-output type output select circuit (16) for selecting either the output signal of the combinational logic circuit (13) or the output signal of the clock-synchronized circuit (14), depending on the stored data in the data memory circuit (10).

公开(公告)号：EP0372749B1

公开(公告)日：1994-09-21

申请号：EP89312115.2

申请日：1989-11-22

申请人： Pilkington Micro-Electronics Limited

发明人： Cliff, Richard Guy Maud Cottage ,  Austin, Kenneth

IPC分类号： H03K19/173

CPC分类号： H03K19/17792 ,  H03K19/173 ,  H03K19/17704 ,  H03K19/17728

公开(公告)号：EP0220816B1

公开(公告)日：1992-06-10

申请号：EP86306965.4

申请日：1986-09-10

申请人： Pilkington Micro-Electronics Limited

发明人： Austin, Kenneth

IPC分类号： H03K17/687

CPC分类号： H03K19/1778 ,  G06F17/5027 ,  H03K5/026 ,  H03K17/687 ,  H03K19/1733 ,  H03K19/1736 ,  H03K19/17704

公开(公告)号：EP0260033B1

公开(公告)日：1992-03-04

申请号：EP87307599.8

申请日：1987-08-27

申请人： Pilkington Micro-Electronics Limited

发明人： Austin, Kenneth

IPC分类号： H03K17/60 ,  H03K19/173

CPC分类号： H03K17/602 ,  H03K19/1736

公开(公告)号：EP0450866A3

公开(公告)日：1992-01-02

申请号：EP91302730.6

申请日：1991-03-27

申请人： Pilkington Micro-Electronics Limited

发明人： Austin, Kenneth

IPC分类号： G11C27/02 ,  H03H11/48

CPC分类号： G11C27/024 ,  G11C27/00 ,  G11C27/026

摘要： This invention relates to semiconductor integrated circuits concerned with the realisation of different value capacitive components of a semiconductor chip by means of programming control arrangements. Programmable (IC) capacitors are implemented using a capacitive multiplier technique. Programmable capacitors comprise essentially three elements, a capacitor (C1) and one or two capacitor multipliers (M1 and M2). Capacitor (C1) is connected to the output of a first buffer circuit (B1) while programmable resistors (RP1 and RP2) are connected in series between the input and output of the buffer (B1), an output being taken from the junction between the first and second programmable resistors. By this arrangement of components, the ratio of the set values of the two programmable resistors (RP2 and RP1) determines the amount by which the capacitor (C1) value is multiplied. An overall effective capacitance value equal to (RP2/RP1) x C1 may be achieved. The final effective capacitance with two multipliers (M1, M2) approximates to (RP2/RP1) x (RP4/RP3) x C1. The value of programmable resistor RP1 is adjusted in accordance with an analogue reference signal (CCV) produced by a compensating circuit (Fig 2) to compensate for the manufacturing/processing variations of capacitor C1.