公开(公告)号：EP1459362A2

公开(公告)日：2004-09-22

申请号：EP02790389.7

申请日：2002-11-16

申请人： Aixtron AG

发明人： JÜRGENSEN, Holger ,  KROST, Alois ,  DADGAR, Armin

IPC分类号： H01L21/20 ,  H01L33/00 ,  C30B25/02 ,  H01L21/762

CPC分类号： C30B23/02 ,  C30B25/02 ,  C30B25/18 ,  C30B29/40 ,  C30B29/406 ,  H01L21/02381 ,  H01L21/02455 ,  H01L21/02463 ,  H01L21/02538 ,  H01L21/0262

摘要： The invention relates to a method for depositing thick III-V semiconductor layers on a non-III-V substrate, particularly a silicon substrate, by introducing gaseous starting materials into the process chamber of a reactor. The aim of the invention is to carry out the crystalline deposition of thick III-V semiconductor layers on a silicon substrate without the occurrence of unfavorable lattice distortions. To this end, the invention provides that a thin intermediate layer is deposited at a reduced growth temperature between two III-V layers.

公开(公告)号：EP1259978A2

公开(公告)日：2002-11-27

申请号：EP01921151.5

申请日：2001-03-02

申请人： Aixtron AG

发明人： DADGAR, Armin ,  KROST, Alois ,  HEUKEN, Michael ,  ALAM, Assadulah ,  SCHÖN, Oliver

IPC分类号： H01L21/205

CPC分类号： C30B25/02 ,  C30B29/403 ,  C30B29/406 ,  H01L21/02381 ,  H01L21/0254 ,  H01L21/0262

摘要： The invention relates to a method and a device for producing Group-III-N, Group-III-V-N and metal-nitrogen component structures on Si substrates by means of organometallic gas phase epitaxy. The inventive method and the corresponding device are characterised in that a low-temperature germination layer and/or a low-temperature buffer layer is/are produced from a Group III-V semiconductor and/or a metal-Group V connecting semiconductor and a component layer or sequence of layers is produced from Group-III-N, Group-III-V-N or metal-Group-V semiconductors in a horizontal growth chamber, in that a minimal lateral temperature difference of less than 5 K, preferably less than 1K, an adjustable roof temperature and/or wall temperature and a temperature on a substrate holder that is caused to rotate by a gas cushion are maintained, the reaction gases being introduced in such a way as to prevent any unwanted interaction between the starting gases and in such a way that the procedure can be observed without disturbing the growth process.

摘要翻译： 本发明涉及通过有机金属气相外延在Si衬底上制造III族-N族，III族-V-N族和金属 - 氮组分结构的方法和装置。 本发明的方法和相应的装置的特征在于，由III-V族半导体和/或金属-V族连接半导体和组分制备低温发芽层和/或低温缓冲层 层或层序列由水平生长室中的III族-N族，III族-VN族或V族金属半导体产生，其中小于5K，优选小于1K的最小侧向温度差， 保持可调整的顶部温度和/或壁温以及通过气垫导致旋转的衬底支架上的温度，反应气体以防止起始气体之间的任何不希望的相互作用的方式引入，并且在这种情况下 可以在不影响生长过程的情况下观察程序。

公开(公告)号：EP1459365A2

公开(公告)日：2004-09-22

申请号：EP02805280.1

申请日：2002-11-15

申请人： Aixtron AG

发明人： JÜRGENSEN, Holger ,  KROST, Alois ,  DADGAR, Armin

IPC分类号： H01L21/20 ,  H01S5/02 ,  C30B25/02

CPC分类号： H01S5/32341 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01S5/021

摘要： The invention relates to a method for the production of III-V laser components, whereby a III-V semiconductor layer is deposited on a silicon substrate in a process chamber of a reactor from a gaseous starting material. According to the invention, an economical method for the production of qualitatively high-grade laser may be achieved, whereby, firstly, an Al-containing buffer layer is deposited on the Si substrate, in particular a Si(III) substrate, on which the III-V semiconductor layer, in particular, GaN layer is then deposited such that the lattice plane thereof runs parallel to the cleavage direction of the substrate, whereby, on cleaving the substrate plane-parallel layer, cleavage surfaces are formed.

公开(公告)号：EP1456872A1

公开(公告)日：2004-09-15

申请号：EP02792976.9

申请日：2002-12-11

申请人： Aixtron AG

发明人： JÜRGENSEN, Holger ,  KROST, Alois ,  DADGAR, Armin

IPC分类号： H01L21/203 ,  C30B25/04 ,  C30B25/08

CPC分类号： C30B25/02 ,  C30B25/18 ,  C30B29/40 ,  C30B29/403 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02463 ,  H01L21/02502 ,  H01L21/02538 ,  H01L21/02639 ,  H01L21/02647

摘要： The invention relates to a method for depositing III-V semiconductor layers on a non III-V substrate, especially a sapphire, silicon or silicon oxide substrate, or another substrate containing silicon. According to said method, a III-V layer, especially a buffer layer, is deposited on the substrate or on a III-V germination layer, in a process chamber of a reactor containing gaseous starting materials. In order to reduce the defect density of the overgrowth, a masking layer consisting of an essentially amorphous material is deposited directly on the III-V germination layer or directly on the substrate, said masking layer partially covering or approximately partially covering the germination layer. The masking layer can be a quasi-monolayer and can consist of various materials.

摘要翻译： 本发明涉及用于在非III-V衬底，特别是蓝宝石，硅或氧化硅衬底，或含硅的另一衬底上沉积III-V族半导体层的方法。 根据所述方法，在含有气态起始材料的反应器的处理室中，将III-V层，特别是缓冲层沉积在衬底上或III-V发芽层上。 为了减少过度生长的缺陷密度，将由基本上无定形的材料组成的掩蔽层直接沉积在III-V发芽层上或直接沉积在基底上，所述掩蔽层部分覆盖或部分覆盖发芽层。 掩蔽层可以是准单层并且可以由各种材料组成。