A computer apparatus having a means to force sequential instruction execution
    2.
    发明公开
    A computer apparatus having a means to force sequential instruction execution 失效
    一种计算设备,包括用于迫使指令的执行以规则序列的含义。

    公开(公告)号:EP0679990A1

    公开(公告)日:1995-11-02

    申请号:EP94118879.9

    申请日:1994-11-30

    IPC分类号: G06F9/38 G06F9/46

    摘要: SA computer apparatus which detects a store or load operation into or from a shared memory page (809) by a program that does not provide for synchronization when executed by a CPU that completes instructions out of program order. After the store or load is detected, the CPU explicitly orders operations into the shared memory page. Store operations are ordered such that no new store (815) into the shared memory page (809) is performed until all prior store operations (813) into the shared memory page (809) are complete. Also, load operations are ordered such that load operations from the shared memory page (809) are performed in program order. This ordering is achieved by maintaining a process bit (811) and a memory attribute bit (819) associated with a shared memory page (809). When both bits (811, 819) are true, all load or store operations referencing the shared memory page (809) are ordered.

    摘要翻译: 其检测存储或加载运行中或从一个共享存储器页(809)由一个程序并不同步时提供由CPU执行做SA计算机装置完成指令按程序顺序。 当检测到存储或加载之后,CPU明确订购操作到共享存储器页面。 存储操作是有序的搜索没有任何新的商店(815)复制到共享内存页(809)执行,直到所有之前的存储操作(813)复制到共享内存页(809)完成。 因此,加载操作进行排序的搜索没有从共享内存页(809)负荷运行程序的顺序执行。 这个顺序由维护处理位(811),并用一个共享存储器页(809)相关联的存储器属性位(819)来实现的。 当这两个位(811,819)是真实的,它引用了共享内存页(809)所有加载或存储操作是有序的。

    Translation mechanism for input/output addresses
    7.
    发明公开
    Translation mechanism for input/output addresses 失效
    ÜbersetzungsmechanismusfürEin- / Ausgabeadressen。

    公开(公告)号:EP0674269A3

    公开(公告)日:1996-06-26

    申请号:EP94114618.5

    申请日:1994-09-16

    IPC分类号: G06F12/10 G06F12/02

    摘要: A computing system includes a first interconnect means (9), a second interconnect means (14), a main memory (12), and an input/output adapter (13). The first interconnect means (9) provides information transfer. For example the first interconnect means (9) is a memory bus. The second interconnect means (14) also provides information transfer. For example the second interconnect means (14) is an input/output bus onto which is connected input/output devices. The main memory (12) is connected to the first interconnect means (9). The main memory (12) includes a page directory (20). The page directory (20) stores translations. Each translation in the page directory (20) includes a portion of an address for data transferred over the second interconnect means (14), for example, the page address portion of I/O bus address. Each translation in the page directory (20) also is indexed by a portion of an address for a memory location within the main memory (12), for example, the page address portion of the address for the memory location. The input/output adapter (13) is connected to the first interconnect means (9) and the second interconnect means (14). The input/output adapter (13) includes a input/output translation look-aside buffer (19). The input/output translation look-aside buffer (19) includes a portion of the translations stored in the page directory (20).

    摘要翻译: 计算系统包括第一互连装置(9),第二互连装置(14),主存储器(12)和输入/输出适配器(13)。 第一互连装置(9)提供信息传送。 例如,第一互连装置(9)是存储器总线。 第二互连装置(14)还提供信息传送。 例如,第二互连装置(14)是其上连接有输入/输出装置的输入/输出总线。 主存储器(12)连接到第一互连装置(9)。 主存储器(12)包括页目录(20)。 页面目录(20)存储翻译。 页目录(20)中的每个翻译包括通过第二互连装置(14)传送的数据的地址的一部分,例如I / O总线地址的页地址部分。 页目录(20)中的每个翻译也由主存储器(12)内的存储器位置的一部分地址索引,例如存储器位置的地址的页地址部分。 输入/输出适配器(13)连接到第一互连装置(9)和第二互连装置(14)。 输入/输出适配器(13)包括输入/​​输出转换后备缓冲器(19)。 输入/输出转换后备缓冲器(19)包括存储在页目录(20)中的一部分翻译。