摘要:
SA computer apparatus which detects a store or load operation into or from a shared memory page (809) by a program that does not provide for synchronization when executed by a CPU that completes instructions out of program order. After the store or load is detected, the CPU explicitly orders operations into the shared memory page. Store operations are ordered such that no new store (815) into the shared memory page (809) is performed until all prior store operations (813) into the shared memory page (809) are complete. Also, load operations are ordered such that load operations from the shared memory page (809) are performed in program order. This ordering is achieved by maintaining a process bit (811) and a memory attribute bit (819) associated with a shared memory page (809). When both bits (811, 819) are true, all load or store operations referencing the shared memory page (809) are ordered.
摘要:
A method for operating a digital computer in response to the occurrence of an exception is disclosed. The method provides for the examination both of the contents of a predetermined computer location and of the instruction code for the instruction causing the exception. The computer then utilizes the results of those examinations to determine the dismissibility of the exception. The computer transfers control to the next instruction after the instruction which caused the exception if that instruction is dismissible.
摘要:
A computing system includes a first interconnect means (9), a second interconnect means (14), a main memory (12), and an input/output adapter (13). The first interconnect means (9) provides information transfer. For example the first interconnect means (9) is a memory bus. The second interconnect means (14) also provides information transfer. For example the second interconnect means (14) is an input/output bus onto which is connected input/output devices. The main memory (12) is connected to the first interconnect means (9). The main memory (12) includes a page directory (20). The page directory (20) stores translations. Each translation in the page directory (20) includes a portion of an address for data transferred over the second interconnect means (14), for example, the page address portion of I/O bus address. Each translation in the page directory (20) also is indexed by a portion of an address for a memory location within the main memory (12), for example, the page address portion of the address for the memory location. The input/output adapter (13) is connected to the first interconnect means (9) and the second interconnect means (14). The input/output adapter (13) includes a input/output translation look-aside buffer (19). The input/output translation look-aside buffer (19) includes a portion of the translations stored in the page directory (20).
摘要:
A computer apparatus incorporating special instructions to force load and store operations to execute in program order. The present invention provides a new and novel store instruction that is suspended until all prior store instructions have been completed by an associated CPU. Also, a new load instruction is provided which blocks any subsequent load instructions from executing until this load instruction has been completed by an associated CPU. These instructions allow for high efficiency computer systems to be implemented which optimize instruction throughput by executing subsequent instructions while waiting for a prior instruction to complete.
摘要:
A computing system includes a main memory and an input/output adapter. The input/output adapter accesses a translation map. The translation map maps input/output page numbers to memory address page numbers. Entries to the translation map are generated so that each entry includes an address of a data page in the main memory and transaction configuration information. The transaction configuration information is utilized by the input/output adapter during data transactions to and from the data page.