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公开(公告)号：EP0531707A3
公开(公告)日：1995-05-17
申请号：EP92113264.3
申请日：1992-08-04
IPC分类号： H01L27/115 , G11C16/02
CPC分类号： H01L27/115
摘要： A memory cell (10, 50), suitable for electrically erasable programmable read only memories (EEPROMs), which has direct write cell capability is disclosed. The memory cell (10, 50) is fabricated on a substrate (12, 52) and uses an inversion source gate (18, 54) disposed above the substrate (12, 52) to generate a depletion source (IS) therein. The depletion source (IS) defines a channel region in the substrate (12, 52) with an associated drain (14, ID). An electrically isolated floating gate (26, 62) is disposed above the substrate (12, 52) so as to overlap at least a portion of the substrate channel region. Further, a program gate (30, 66) is disposed to overlap a portion of the floating gate (26, 62) and an access gate (34, 70) is also provided aligned at least partially over the substrate channel region such that a dual gate device is defined. An array of such memory cells (10, 50) is also disclosed.
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公开(公告)号：EP0176714A3
公开(公告)日：1987-10-14
申请号：EP85110140
申请日：1985-08-13
发明人： Lam, Chung Hon
CPC分类号： G11C14/00 , H01L29/7882
摘要： A non-volatile dynamic memory cell in which the non-volatile element has two different areas for electron injection, such that direct overwriting of previously stored non-volatile data is permitted without an intervening erase cycle. The non-volatile storage element is a floating gate electrode (16) which has dual contro gates (24, 26) disposed thereon. Each control gate (24, 261 includes a layer (20A, 20B) of dual electron injector structure (DEIS) material and a polysilicon layer. When writing a "0" from the volatile storage capacitor (20,14A, 26) to the floating gate (16), one of the control gates (24, 26) removes charge from the floating gate (16). To write a "1", the other control gate injects charge into the floating gate (16). The above charge transfer does not take place if the previously stored logic gate and the logic state to be written in are identical.
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公开(公告)号：EP0175894A3
公开(公告)日：1987-10-14
申请号：EP85109848
申请日：1985-08-06
CPC分类号： H01L29/7882
摘要： A non-volatile storage cell uses two different areas (28A, 28B) for electron injection, allowing direct overwriting of previously stored data without an intervening erase cycle. A floating gate FET has duel programming gates (PG1, PG2) disposed on its floating gate (22). Each programming gate (PG1, PG2) includes n layer (28A, 28B) of dual electron injector structure (DEIS) and a polysilicon electrode (30, 32). When writing a "0", one of the programming gates PG1, PG2) removes charge from the floating gate (22). When writing "1", the other programming gate injects charge into the floating gate (22). This charge transfer does not take place if the previously stored logic state and the logic state to be written in are identical.
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公开(公告)号：EP0543158A3
公开(公告)日：1993-12-29
申请号：EP92117856.2
申请日：1992-10-19
发明人： Lam, Chung Hon , Lasky, Jerome Brett , Hill, Craig Marshall , Nakos, James Spiros , Holmes, Steven John , Geissler, Stephen Frank , Lord, David Kennedy
IPC分类号： H01L21/90
CPC分类号： H01L21/32134 , H01L21/768
摘要： The invention provides a method for electrically connecting a polysilicon-filled trench (12) to a diffusion region (10) in a semiconductor device, wherein the trench (12) and diffusion region (10) are separated by a dielectric (14). The method provides for formation of a strap or bridge contact by utilizing a diffusion barrier layer (18) which prevents diffusion into an overlying polysilicon layer (32) when a subsequent boron (16) out-diffusion step is performed. Selective etching is then utilized to remove the polysilicon layer (32) where no boron has diffused, leaving a polysilicon strap connecting the trench and diffusion region.
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公开(公告)号：EP0175894B1
公开(公告)日：1992-10-21
申请号：EP85109848.3
申请日：1985-08-06
IPC分类号： H01L29/60 , H01L29/788 , G11C17/00
CPC分类号： H01L29/7882
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6.发明公开Memory cell storing logic data in volatile and non-volatile forms 失效Speicherzelle zum Speichern logischer Daten inflüchtigerundnichtflüchtigerWeise。
公开(公告)号：EP0176714A2
公开(公告)日：1986-04-09
申请号：EP85110140.2
申请日：1985-08-13
发明人： Lam, Chung Hon
CPC分类号： G11C14/00 , H01L29/7882
摘要： A non-volatile dynamic memory cell in which the non-volatile element has two different areas for electron injection, such that direct overwriting of previously stored non-volatile data is permitted without an intervening erase cycle. The non-volatile storage element is a floating gate electrode (16) which has dual contro gates (24, 26) disposed thereon. Each control gate (24, 261 includes a layer (20A, 20B) of dual electron injector structure (DEIS) material and a polysilicon layer. When writing a "0" from the volatile storage capacitor (20,14A, 26) to the floating gate (16), one of the control gates (24, 26) removes charge from the floating gate (16). To write a "1", the other control gate injects charge into the floating gate (16). The above charge transfer does not take place if the previously stored logic gate and the logic state to be written in are identical.
摘要翻译： 非易失性动态存储单元，其中非易失性元件具有用于电子注入的两个不同区域，使得允许直接覆盖先前存储的非易失性数据而不需要中间擦除周期。 非易失性存储元件是浮置栅电极（16），其上设置有双重控制门（24,26）。 每个控制栅极（24,26）包括双电子注入器结构（DEIS）材料的层（20A，20B）和多晶硅层。 当从易失性存储电容器（20,14A，26）写入“0”到浮动栅极（16）时，其中一个控制栅极（24,26）从浮动栅极（16）去除电荷。 为了写入“1”，其他控制栅极将电荷注入到浮动栅极（16）中。 如果先前存储的逻辑门和要写入的逻辑状态相同，则不会发生上述电荷转移。
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公开(公告)号：EP0055803A3
公开(公告)日：1983-11-09
申请号：EP81108551
申请日：1981-10-20
CPC分类号： G11C16/0433
摘要： A memory system, particularly an electrically alterable read only memory system which includes a semiconductor substrate (10) having a diffusion region (12) therein defining one end of a channel region (14), a control plate (22, T1), a floating plate (20) separated from the channel region by a thin dielectric layer (16) and disposed between the control plate (22) and the channel region (14) and means (T1-T3) for transferring charge to and from the floating plate (22). A control gate (32) is coupled to the channel region (14) and is located between the diffusion region (12) and the floating plate (22). The control gate (32) may be connected to a word line and the diffusion region (12) may be connected to a bit/sense line. The channel region (14) is controlled by the word line and the presence or absence of charge on the floating plate (20). Thus, information may be read from a cell of the memory by detecting the presence or absence of charge stored in the inversion capacitor under the floating plate (20). The charge transfer means (T1-T3) includes an enhanced conduction insulator (24) and means (T1, T3) for applying appropriate voltages to the control plate (22) and to the control gate (32) to transfer charge to and from the floating plate (20) through the enhanced conduction insulator (24).
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8.发明公开Method of conducting strap formation in a semiconductor device 失效Herstellungsverfahren von einer leitenden Verbindung in einer Halbleitervorrichtung。
公开(公告)号：EP0543158A2
公开(公告)日：1993-05-26
申请号：EP92117856.2
申请日：1992-10-19
发明人： Lam, Chung Hon , Lasky, Jerome Brett , Hill, Craig Marshall , Nakos, James Spiros , Holmes, Steven John , Geissler, Stephen Frank , Lord, David Kennedy
IPC分类号： H01L21/90
CPC分类号： H01L21/32134 , H01L21/768
摘要： The invention provides a method for electrically connecting a polysilicon-filled trench (12) to a diffusion region (10) in a semiconductor device, wherein the trench (12) and diffusion region (10) are separated by a dielectric (14). The method provides for formation of a strap or bridge contact by utilizing a diffusion barrier layer (18) which prevents diffusion into an overlying polysilicon layer (32) when a subsequent boron (16) out-diffusion step is performed. Selective etching is then utilized to remove the polysilicon layer (32) where no boron has diffused, leaving a polysilicon strap connecting the trench and diffusion region.
摘要翻译： 本发明提供了一种用于将多晶硅填充的沟槽（12）电连接到半导体器件中的扩散区（10）的方法，其中沟槽（12）和扩散区（10）由电介质（14）分开。 该方法通过利用当执行随后的硼（16）扩散步骤时阻止扩散到上覆多晶硅层（32）中的扩散阻挡层（18）来形成带或桥接触。 然后利用选择性蚀刻来除去其中没有硼扩散的多晶硅层（32），留下连接沟槽和扩散区域的多晶硅条带。
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