公开(公告)号：EP4404258A1

公开(公告)日：2024-07-24

申请号：EP22869569.8

申请日：2022-01-31

Applicant: Sony Semiconductor Solutions Corporation

Inventor： FUJII, Nobutoshi

IPC: H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L25/065 ,  H01L23/522 ,  H01L21/3205 ,  H01L21/768 ,  H01L25/18 ,  H01L25/07

Abstract: To prevent a metal embedding defect in a semiconductor device in which a through-via is formed.
The semiconductor device includes a substrate, an etching stopper layer, a die, and an isolation film. In the semiconductor device, a rewiring layer is formed on the substrate. The etching stopper layer is formed on a bonding surface of the rewiring layer. The die is bonded to a partial region of the bonding surface via the etching stopper layer. The isolation film covers the die and the etching stopper layer.

公开(公告)号：EP3370252A1

公开(公告)日：2018-09-05

申请号：EP15907235.4

申请日：2015-10-28

Applicant: OLYMPUS CORPORATION

Inventor： SUYAMA Takuro

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5226 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/76802 ,  H01L23/522

Abstract: A semiconductor apparatus 1 includes a semiconductor device 10 having a semiconductor circuit 11 formed on a first main surface 10SA, and including a via H10 having an opening at a second main surface 10SB, a first wiring 21A disposed on the first main surface 10SA of the semiconductor device 10, partially exposed at a bottom surface of the via H10, and connected to the semiconductor circuit 11, a first insulating layer 22A covering the first wiring 21A, and a redistribution wiring 30 extending from a contact portion 30A in contact with the first wiring 21A at the bottom surface of the via H10, through an inside of the via H10 and onto the second main surface 10SB, where a first through hole H21A is formed in the first wiring 21A, and the contact portion 30A is in contact with a plurality of surfaces of the first wiring 21A.

公开(公告)号：EP3356288A1

公开(公告)日：2018-08-08

申请号：EP16852584.8

申请日：2016-09-29

Applicant: Mems Drive Inc.

Inventor： GUTIERREZ, Roman ,  TANG, Tony ,  LIU, Xiaolei ,  WANG, Guiqin ,  NG, Matthew

IPC: B81B7/04 ,  B81B5/00 ,  B81B3/00

CPC classification number: H01L21/76816 ,  B81B3/0045 ,  B81B7/0029 ,  B81B2203/0353 ,  B81C1/00674 ,  B81C1/00682 ,  B81C2201/0112 ,  B81C2201/0135 ,  H01L21/768 ,  H01L21/76898 ,  H01L23/485 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/1461 ,  H01L2924/181

Abstract: A system and method for manipulating the structural characteristics of a MEMS device include etching a plurality of holes into the surface of a MEMS device, wherein the plurality of holes comprise one or more geometric shapes determined to provide specific structural characteristics desired in the MEMS device.

公开(公告)号：EP3223311A4

公开(公告)日：2018-06-20

申请号：EP15778189

申请日：2015-03-23

Applicant: BOE TECHNOLOGY GROUP CO LTD

Inventor： ZHANG XIANGYAN ,  WU YANBING ,  LI WENBO ,  LI PAN ,  JIA QIAN

IPC: H01L27/02 ,  H01L21/82 ,  H01L23/50

CPC classification number: G02F1/136286 ,  G02F1/133345 ,  G02F1/133528 ,  G02F1/13439 ,  G02F1/136227 ,  G02F2001/133548 ,  G02F2001/13629 ,  G02F2001/136295 ,  G02F2201/123 ,  H01L21/768 ,  H01L21/82 ,  H01L21/84 ,  H01L23/481 ,  H01L23/50 ,  H01L27/124 ,  H01L27/1259 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The embodiments of the present invention provide a substrate and a manufacturing method thereof, as well as a display device. The substrate comprises: a base substrate, a plurality of gate lines arranged in parallel, a first insulating layer that covers the gate lines, a plurality of data lines located on the first insulating layer and perpendicular to the gate lines, a second insulating layer that covers the data lines, and pixel electrodes of sub-pixel areas enclosed by the data lines and the gate lines; polarizing films that cover the pixel electrodes; and first auxiliary gate lines arranged on the second insulating layer and parallel to the gate lines, at least two portions on each of the first auxiliary gate lines being electrically connected with at least two corresponding portions on the gate line through via holes that penetrate the first insulating layer and the second insulating layer, the first auxiliary gate lines and the polarizing films are formed by performing a same patterning process to a same layer of transparent conductive material. The embodiments of the present invention can reduce signal delay in a display device, and can be used for manufacture of a display.

公开(公告)号：EP3331000A1

公开(公告)日：2018-06-06

申请号：EP17275192.7

申请日：2017-12-04

Applicant: SPTS Technologies Limited

Inventor： MUMFORD, Roland

IPC: H01L21/3065 ,  H01L21/768

CPC classification number: H01L21/3065 ,  H01L21/67069 ,  H01L21/768 ,  H01L21/76898

Abstract: According to the invention there is provided a method of smoothing a surface of a silicon substrate comprising the steps of: providing a silicon substrate having a backside surface, wherein the silicon substrate has been ground to leave the backside surface with an associated roughness; and smoothing the backside surface of the silicon substrate using a plasma etch process; in which the plasma etch process comprises the steps of performing a first plasma etch step which forms a plurality of protrusions that upstand from the backside surface; and performing a second plasma etch step which at least partially etches the protrusions to provide a smoothed backside surface which exhibits specular reflection.

公开(公告)号：EP3279927A1

公开(公告)日：2018-02-07

申请号：EP16773202.3

申请日：2016-03-31

Applicant: Hamamatsu Photonics K.K.

Inventor： ISHIDA Atsushi ,  HOSOKAWA Noburo ,  NAGANO Terumasa ,  BABA Takashi

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L27/14687 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/522 ,  H01L23/532 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14643 ,  H01L31/02005 ,  H01L31/0203 ,  H01L31/02161 ,  H01L31/022408 ,  H01L31/103 ,  H01L31/107 ,  H01L2224/02313 ,  H01L2224/0233 ,  H01L2224/0235 ,  H01L2224/0236 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/02381 ,  H01L2224/0345 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/10126 ,  H01L2224/11 ,  H01L2224/12105 ,  H01L2224/13007 ,  H01L2224/13009 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2924/10253 ,  H01L2924/12043 ,  H01L2924/351 ,  H01L2924/00014

Abstract: A through hole 7 is a vertical hole. When attention is paid to regions on both sides of a center line CL of the through hole 7 in a plane including the center line CL of the through hole, it is assumed that a segment that connects a first point X1 corresponding to the edge of an opening 10a of an insulating layer 10 and a second point X2 corresponding to the edge of a second opening 7b is a first segment S1, a segment that connects the second point X2 and a third point X3 corresponding to an intersection point between the second opening 7b and a surface 10b of the insulating layer 10 is a second segment S2, and a segment that connects the third point X3 and the first point X1 is a third segment S3. In this case, the first area A1 of the insulating layer 10 that is located on one side with respect to the first segment S1 is larger than the sum of the second area A2 of the insulating layer 10 that is surrounded by the first segment S1, the second segment S2, and the third segment S3 and the third area A3 of the insulating layer 10 that is located on the other side with respect to the third segment S3.

Abstract translation: 通孔7是垂直孔。 当关注贯通孔7的中心线CL的两侧的区域时，在包含贯通孔的中心线CL的平面中，假设连接与第一点X1对应的第一点X1 绝缘层10的开口10a和与第二开口7b的边缘相对应的第二点X2是第一段S1，连接第二点X2和对应于第二开口7b之间的交点的第三点X3的段 并且绝缘层10的表面10b是第二段S2，并且连接第三点X3和第一点X1的段是第三段S3。 在这种情况下，绝缘层10的相对于第一段S1位于一侧的第一区域A1大于由第一段S1包围的绝缘层10的第二区域A2的总和， 第二区段S2以及绝缘层10的第三区段S3和第三区域A3，其位于相对于第三区段S3的另一侧。

公开(公告)号：EP3229261A1

公开(公告)日：2017-10-11

申请号：EP17163844.8

申请日：2017-03-30

Applicant: Semiconductor Manufacturing International Corporation (Shanghai) ,  Semiconductor Manufacturing International Corporation (Beijing)

Inventor： LI, Haiting

IPC: H01L21/02 ,  H01L21/762

CPC classification number: H01L23/60 ,  H01L21/02002 ,  H01L21/265 ,  H01L21/76251 ,  H01L21/768 ,  H01L21/823437

Abstract: A method for fabricating a semiconductor structure includes providing a wafer and a carrier wafer. The wafer includes a first bonding surface and a plurality of radio-frequency (RF) devices and the carrier wafer includes a second bonding surface. The method further includes performing a surface treatment process on the second bonding surface to convert a surface portion of the carrier wafer into a barrier layer to suppress movement of induced electrical charges in the carrier wafer, and then bonding the wafer with the carrier wafer through the first bonding surface and the second bonding surface, respectively.

Abstract translation: 用于制造半导体结构的方法包括提供晶片和载体晶片。 晶片包括第一键合表面和多个射频（RF）器件，并且载体晶片包括第二键合表面。 该方法还包括在第二接合表面上执行表面处理工艺以将载体晶圆的表面部分转变为阻挡层以抑制载体晶圆中的感应电荷的移动，然后通过 第一结合表面和第二结合表面。

公开(公告)号：EP3216055A1

公开(公告)日：2017-09-13

申请号：EP15794782.1

申请日：2015-11-05

Applicant: Qualcomm Incorporated

Inventor： LEE, Jae Sik ,  WE, Hong Bok ,  KIM, Dong Wook ,  GU, Shiqun

IPC: H01L23/538

CPC classification number: H01L23/5389 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L23/3107 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/19 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/73209 ,  H01L2224/81005 ,  H01L2224/92124 ,  H01L2924/15192 ,  H01L2924/18161 ,  H01L2924/18162

Abstract: Some novel features pertain to an integrated device package that includes an encapsulation portion and a redistribution portion. The encapsulation portion includes a first die, a first set of vias coupled to the first die, a second die, a second set of vias coupled to the second die, a bridge, and an encapsulation layer. The bridge is configured to provide an electrical path between the first die and the second die. The bridge is coupled to the first die through the first set of vias. The bridge is further coupled to the second die through the second set of vias. The encapsulation layer at least partially encapsulates the first die, the second die, the bridge, the first set of vias, and the second set of vias. The redistribution portion is coupled to the encapsulation portion. The redistribution portion includes a set of redistribution interconnects, and at least one dielectric layer.

Abstract translation: 一些新颖的特征涉及包括封装部分和再分布部分的集成器件封装。 封装部分包括第一裸片，耦合到第一裸片的第一组通孔，第二裸片，耦合到第二裸片的第二组通孔，桥和封装层。 桥被配置为在第一管芯和第二管芯之间提供电路径。 桥通过第一组通孔耦合到第一管芯。 该桥通过第二组通孔进一步耦合到第二管芯。 封装层至少部分封装第一管芯，第二管芯，桥，第一组通孔和第二组通孔。 再分布部分连接到封装部分。 再分布部分包括一组再分布互连和至少一个介电层。

公开(公告)号：EP3132470A1

公开(公告)日：2017-02-22

申请号：EP15721395.0

申请日：2015-04-17

Applicant: Butterfly Network Inc.

Inventor： ROTHBERG, Jonathan, M. ,  FIFE, Keith, G. ,  SANCHEZ, Nevada, J. ,  ALIE, Susan, A.

IPC: H01L27/06 ,  H01L21/768 ,  B81C1/00 ,  A61B8/00 ,  A61B5/02 ,  B06B1/02 ,  H01L27/092

CPC classification number: H01L27/0617 ,  A61B8/00 ,  A61B8/4494 ,  B06B1/02 ,  B06B1/0292 ,  B06B2201/51 ,  B81B3/0021 ,  B81B7/0006 ,  B81B2201/0271 ,  B81C1/00158 ,  B81C1/00246 ,  B81C2203/0735 ,  B81C2203/0771 ,  H01L21/32134 ,  H01L21/56 ,  H01L21/768 ,  H01L21/76838 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0688 ,  H01L27/092 ,  H01L2224/16225

Abstract: Micromachined ultrasonic transducers formed in complementary metal oxide semiconductor (CMOS) wafers are described, as are methods of fabricating such devices. A metallization layer of a CMOS wafer may be removed by sacrificial release to create a cavity of an ultrasonic transducer. Remaining layers may form a membrane of the ultrasonic transducer.

Abstract translation: 还描述了形成在互补金属氧化物半导体（CMOS）晶片中的微加工超声换能器，以及制造这种器件的方法。 可以通过牺牲释放去除CMOS晶片的金属化层以产生超声换能器的空腔。 剩余的层可以形成超声换能器的膜。

公开(公告)号：EP3031775A1

公开(公告)日：2016-06-15

申请号：EP15198177.6

申请日：2015-12-07

Applicant: Commissariat à l'Énergie Atomique et aux Énergies Alternatives

Inventor： NICOLAS, Stéphane ,  FANGET, Stéphane

IPC: B81C1/00 ,  H01L23/498

CPC classification number: H01L24/75 ,  B81C1/00238 ,  B81C2203/0792 ,  H01L21/768 ,  H01L23/49816

Abstract: Procédé comprenant des étapes consistant à :
a) déposer une bille fusible (16a, 16b) sur une première zone conductrice (6a, 6b) située dans un trou borgne formé au niveau d'une première face d'un premier support (1),
b) assembler le premier support (1) avec un deuxième support (100) par report de la bille fusible (16a, 16b) sur une deuxième zone conductrice (126a, 126b), le report étant en outre réalisé par thermo-compression de sorte à écraser la bille, la bille écrasée étant maintenue à distance (Δ') des parois latérales du trou borgne.