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    COMPARISON OPERATIONS IN MEMORY
    1.
    发明公开
    COMPARISON OPERATIONS IN MEMORY 审中-公开
    记忆中的比较操作

    公开(公告)号：EP3167448A2

    公开(公告)日：2017-05-17

    申请号：EP15802782.1

    申请日：2015-06-02

    申请人： Micron Technology, Inc.

    发明人： WHEELER, Kyle B. ,  MANNING, Troy A. ,  MURPHY, Richard C.

    IPC分类号： G11C7/06 ,  G11C7/10

    CPC分类号： G11C11/4091 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1012 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4093 ,  G11C11/4096

    摘要： One example of the present disclosure includes performing a comparison operation in memory using a logical representation of a first value stored in a first portion of a number of memory cells coupled to a sense line of a memory array and a logical representation of a second value stored in a second portion of the number of memory cells coupled to the sense line of the memory array. The comparison operation compares the first value to the second value, and the method can include storing a logical representation of a result of the comparison operation in a third portion of the number of memory cells coupled to the sense line of the memory array.

    摘要翻译： 本公开的一个示例包括使用存储在耦合到存储器阵列的感测线的多个存储器单元的第一部分中的第一值的逻辑表示和存储的第二值的逻辑表示的存储器中执行比较操作 在耦合到存储器阵列的感测线的多个存储器单元的第二部分中。 比较操作将第一值与第二值进行比较，并且该方法可以包括将比较操作的结果的逻辑表示存储在耦合到存储器阵列的感测线的多个存储器单元的第三部分中。

    SWAP OPERATIONS IN MEMORY
    3.
    发明公开
    SWAP OPERATIONS IN MEMORY 审中-公开
    记忆中的交换操作

    公开(公告)号：EP3195315A1

    公开(公告)日：2017-07-26

    申请号：EP15838692.0

    申请日：2015-09-03

    申请人： Micron Technology, Inc.

    发明人： WHEELER, Kyle B.

    IPC分类号： G11C7/06 ,  G11C7/10 ,  G06F12/02

    CPC分类号： G06F12/0246 ,  G06F1/3275 ,  G06F9/30032 ,  G06F9/3004 ,  G06F12/0207 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1009 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4091 ,  Y02D10/14

    摘要： Examples of the present disclosure provide apparatuses and methods related to performing swap operations in a memory. An example apparatus might include a first group of memory cells coupled to a first sense line and configured to store a first element. An example apparatus might also include a second group of memory cells coupled to a second sense line and configured to store a second element. An example apparatus might also include a controller configured to cause the first element to be stored in the second group of memory cells and the second element to be stored in the first group of memory cells by controlling sensing circuitry to perform a number operations without transferring data via an input/output (I/O) line.

    摘要翻译： 本公开的示例提供了涉及在存储器中执行交换操作的设备和方法。 示例装置可以包括耦合到第一感测线并被配置为存储第一元件的第一组存储器单元。 示例装置还可以包括耦合到第二感测线并被配置为存储第二元素的第二组存储器单元。 示例装置还可以包括控制器，该控制器被配置为通过控制感测电路执行数个操作而不传输数据来使得第一元件被存储在第二组存储器单元中并且第二元件被存储在第一组存储器单元中 通过输入/输出（I / O）线。

    VIRTUAL ADDRESS TABLE
    6.
    发明公开
    VIRTUAL ADDRESS TABLE 审中-公开
    VIRTUELLE ADRESSENTABELLE

    公开(公告)号：EP3152665A1

    公开(公告)日：2017-04-12

    申请号：EP15803929.7

    申请日：2015-05-29

    申请人： Micron Technology, Inc.

    发明人： LEIDEL, John D. ,  WHEELER, Kyle B.

    IPC分类号： G06F12/02 ,  G06F12/06

    CPC分类号： G06F12/1009 ,  G06F8/441 ,  G06F9/445 ,  G06F12/02 ,  G06F12/10 ,  G06F2212/657

    摘要： The present disclosure includes apparatuses and methods related to virtual address tables. An example method comprises generating an object file that comprises: an instruction comprising a number of arguments; and an address table comprising a number of indexed address elements. Each one of the number of indexed address elements can correspond to a virtual address of a respective one of the number of arguments, wherein the address table can serves as a target for the number of arguments. The method can include storing the object file in a memory.

    摘要翻译： 本公开包括与虚拟地址表相关的装置和方法。 一种示例性方法包括生成目标文件，该目标文件包括：包含多个参数的指令; 以及包括多个索引地址元素的地址表。 索引地址元素的数目中的每一个可以对应于参数数量中的相应一个的虚拟地址，其中地址表可以用作参数数量的目标。 该方法可以包括将目标文件存储在存储器中。

    DIVISION OPERATIONS FOR MEMORY
    8.
    发明授权
    DIVISION OPERATIONS FOR MEMORY 有权

    公开(公告)号：EP3066665B1

    公开(公告)日：2018-10-24

    申请号：EP14860497.8

    申请日：2014-11-04

    申请人： Micron Technology, Inc.

    发明人： WHEELER, Kyle B.

    IPC分类号： G11C8/06 ,  G11C7/10

    CPC分类号： G06F7/535 ,  G06F5/01 ,  G06F2207/5353

    摘要： Examples of the present disclosure provide apparatuses and methods for performing division operations in a memory. An example apparatus comprises a first address space comprising a first number of memory cells coupled to a sense line and to a first number of select lines wherein the first address space stores a dividend value. A second address space comprises a second number of memory cells coupled to the sense line and to a second number of select lines wherein the second address space stores a divisor value. A third address space comprises a third number of memory cells coupled to the sense line and to a third number of select lines wherein the third address space stores a remainder value. Sensing circuitry can be configured to receive the dividend value and the divisor value, divide the dividend value by the divisor value, and store a remainder result in the third number of memory cells.

    DIVISION OPERATIONS FOR MEMORY
    10.
    发明公开
    DIVISION OPERATIONS FOR MEMORY 审中-公开
    DIVISIONSOPERATIONENFÜRSPEICHER

    公开(公告)号：EP3066665A1

    公开(公告)日：2016-09-14

    申请号：EP14860497.8

    申请日：2014-11-04

    申请人： Micron Technology, Inc.

    发明人： WHEELER, Kyle B.

    IPC分类号： G11C8/06 ,  G11C7/10

    CPC分类号： G06F7/535 ,  G06F5/01 ,  G06F2207/5353

    摘要： Examples of the present disclosure provide apparatuses and methods for performing division operations in a memory. An example apparatus comprises a first address space comprising a first number of memory cells coupled to a sense line and to a first number of select lines wherein the first address space stores a dividend value. A second address space comprises a second number of memory cells coupled to the sense line and to a second number of select lines wherein the second address space stores a divisor value. A third address space comprises a third number of memory cells coupled to the sense line and to a third number of select lines wherein the third address space stores a remainder value. Sensing circuitry can be configured to receive the dividend value and the divisor value, divide the dividend value by the divisor value, and store a remainder result in the third number of memory cells.

    摘要翻译： 本公开的示例提供了用于在存储器中执行划分操作的装置和方法。 示例性设备包括第一地址空间，其包括耦合到感测线路的第一数量的存储器单元和包括第一地址空间存储分红值的第一数量的选择线。 第二地址空间包括耦合到感测线和第二数量的选择线的第二数量的存储器单元，其中第二地址空间存储除数值。 第三地址空间包括耦合到感测线和第三数量的选择线的第三数量的存储器单元，其中第三地址空间存储余数值。 感测电路可以配置为接收除数值和除数值，除数除数除数值，并将剩余结果存储在第三数量的存储单元中。