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    ANORDNUNG MIT STECKBAREN FUNKTIONSEINHEITEN
    2.
    发明授权
    ANORDNUNG MIT STECKBAREN FUNKTIONSEINHEITEN 失效
    ANORDNUNG MIT STECKBAREN FUNKTION SEINHEITEN

    公开(公告)号：EP0674786B1

    公开(公告)日：1997-03-19

    申请号：EP94902605.8

    申请日：1993-12-17

    申请人： SIEMENS AKTIENGESELLSCHAFT

    发明人： ABERT, Michael ,  BLOCK, Siegfried ,  BOZENHARDT, Johannes ,  LEISGNERING, Franz ,  PFATTEICHER, Werner ,  SCHEWE, Franz-Clemens

    IPC分类号： G06F13/40

    CPC分类号： G05B19/0423 ,  G05B2219/21049 ,  G05B2219/21071 ,  G05B2219/21089 ,  G06F12/0684 ,  G06F13/24 ,  G06F13/4072

    摘要： The invention relates to an arrangement with a plurality of plug points (SP1, ..., SP4) which are interconnected via a system bus (SYB) with data and control lines and into which at least one CPU (CP) is plugged and a plurality of functional peripheral devices (PE1, PE2, PE4) can be plugged. The arrangement is constructed in such a way that the CPU (CP) recognises whether functional units (PE1, PE2, PE4) are plugged into the points (SP1, ..., SP4). The invention is applicable to store programmable controls.

    摘要翻译： 本发明涉及一种具有多个插接点（SP1，...，SP4）的装置，所述插接点通过系统总线（SYB）与数据线和控制线互连并且至少一个CPU（CP）被插入其中并且a 可以插入多个功能外围设备（PE1，PE2，PE4）。 该装置以CPU（CP）识别功能单元（PE1，PE2，PE4）是否插入点（SP1，...，SP4）的方式构造。 本发明适用于存储可编程控制。

    ANORDNUNG MIT STECKBAREN FUNKTIONSEINHEITEN
    3.
    发明公开
    ANORDNUNG MIT STECKBAREN FUNKTIONSEINHEITEN 失效
    ANORDNUNG MIT STECKBAREN FUNKTION SEINHEITEN

    公开(公告)号：EP0674785A1

    公开(公告)日：1995-10-04

    申请号：EP94901770.0

    申请日：1993-12-17

    申请人： SIEMENS AKTIENGESELLSCHAFT

    发明人： ABERT, Michael ,  BLOCK, Siegfried ,  BOZENHARDT, Johannes ,  LEIGSNERING, Franz ,  PFATTEICHER, Werner ,  SCHEWE, Franz-Clemens

    IPC分类号： G05B19 ,  G06F13

    CPC分类号： G06F13/4072 ,  G05B19/0423 ,  G06F13/24

    摘要： The invention relates to an arrangement with a plurality of plug points (SP1, ..., SP4) which are interconnected via a system bus (SYB) with data and control lines and into which at least one CPU (CP) is plugged and a plurality of functional peripheral devices (PE1, PE2, PE4) can be plugged. The arrangement is constructed in such a way that the CPU (CP) rapidly recognises a plugged-in in unit triggering an alarm. The invention is applicable to store programmable controls.

    摘要翻译： 本发明涉及一种具有多个插接点（SP1，...，SP4）的装置，所述插接点通过系统总线（SYB）与数据线和控制线互连并且至少一个CPU（CP）被插入其中并且a 可以插入多个功能外围设备（PE1，PE2，PE4）。 这种安排的构造方式使得CPU（CP）能够快速识别出触发警报的插入单元。 本发明适用于存储可编程控制。

    ANORDNUNG ZUR DATENÜBERTRAGUNG MIT EINEM PARALLELEN BUSSYSTEM
    5.
    发明授权
    ANORDNUNG ZUR DATENÜBERTRAGUNG MIT EINEM PARALLELEN BUSSYSTEM 失效
    安排了并行总线系统中数据传输

    公开(公告)号：EP0667014B1

    公开(公告)日：1998-01-07

    申请号：EP93923453.0

    申请日：1993-10-29

    申请人： SIEMENS AKTIENGESELLSCHAFT

    发明人： ABERT, Michael ,  BLOCK, Siegfried ,  BOZENHARDT, Johannes ,  LEIGSNERING, Franz ,  PFATTEICHER, Werner ,  SCHEWE, Franz-Clemens

    IPC分类号： G06F13/378

    CPC分类号： G06F13/368 ,  G06F13/378

    摘要： The invention pertains to a configuration for data transfer with a parallel bus system, consisting of address, data and control buses, and with several units (3, 4, 5, 6) interfacing with them. A first control line (1) is used to send an acknowledge signal (Ready), with which one or more units addressed by a first unit acknowledge accesses in access cycles. A second control line (2) is used to detect addressing errors and accesses to non-existant units and to carry to the first unit an answering signal (SR) from the others indicating whether one of the interfaced units was addressed. To do so the answering signal (SR) has dominant and recessive statuses. During an access cycle only addressed units generate a dominant status. The answering signal (SR) is also used for synchronous multipoint access. The invention is used in bus systems.

    ANORDNUNG ZUR ÜBERTRAGUNG VON DATEN ÜBER EINEN BUS
    6.
    发明公开
    ANORDNUNG ZUR ÜBERTRAGUNG VON DATEN ÜBER EINEN BUS 失效
    安排用于数据上的总线传输。

    公开(公告)号：EP0671033A1

    公开(公告)日：1995-09-13

    申请号：EP94900046.0

    申请日：1993-11-18

    申请人： SIEMENS AKTIENGESELLSCHAFT

    发明人： ABERT, Michael ,  BLOCK, Siegfried ,  BOZENHARDT, Johannes ,  LEIGSNERING, Franz ,  PFATTEICHER, Werner ,  SCHEWE, Franz-Clemens

    IPC分类号： G06F3 ,  G06F13

    CPC分类号： G06F13/4018

    摘要： An arrangement for transmitting data over a bus (2, 6, 7) has a central unit (1, 4, 5) which initiates data transmission and one or several peripheral units (3, 8, 9) linked to each other by the bus. In at least one of the components, besides first control lines and data lines for transmitting a data word having a first data width, further control lines and further data lines for transmitting a data word having a second data width are also provided. These are designed in such a way that components with different data bus widths can communicate with each other by transmission of data words having the smallest existent data width. In automation equipment, the invention allows any combination of components of different classes of capacity. The invention is used in bus systems.

    ANORDNUNG ZUR DATENÜBERTRAGUNG MIT EINEM PARALLELEN BUSSYSTEM
    7.
    发明公开
    ANORDNUNG ZUR DATENÜBERTRAGUNG MIT EINEM PARALLELEN BUSSYSTEM 失效
    安排了并行总线系统中数据传输。

    公开(公告)号：EP0667014A1

    公开(公告)日：1995-08-16

    申请号：EP93923453.0

    申请日：1993-10-29

    申请人： SIEMENS AKTIENGESELLSCHAFT

    发明人： ABERT, Michael ,  BLOCK, Siegfried ,  BOZENHARDT, Johannes ,  LEIGSNERING, Franz ,  PFATTEICHER, Werner ,  SCHEWE, Franz-Clemens

    IPC分类号： G06F13

    CPC分类号： G06F13/368 ,  G06F13/378

    摘要： The invention pertains to a configuration for data transfer with a parallel bus system, consisting of address, data and control buses, and with several units (3, 4, 5, 6) interfacing with them. A first control line (1) is used to send an acknowledge signal (Ready), with which one or more units addressed by a first unit acknowledge accesses in access cycles. A second control line (2) is used to detect addressing errors and accesses to non-existant units and to carry to the first unit an answering signal (SR) from the others indicating whether one of the interfaced units was addressed. To do so the answering signal (SR) has dominant and recessive statuses. During an access cycle only addressed units generate a dominant status. The answering signal (SR) is also used for synchronous multipoint access. The invention is used in bus systems.

    ANORDNUNG MIT STECKBAREN FUNKTIONSEINHEITEN
    8.
    发明授权
    ANORDNUNG MIT STECKBAREN FUNKTIONSEINHEITEN 无效
    可插拔的功能单元安排

    公开(公告)号：EP0670062B1

    公开(公告)日：1997-09-17

    申请号：EP93924525.4

    申请日：1993-11-18

    申请人： SIEMENS AKTIENGESELLSCHAFT

    发明人： ABERT, Michael ,  BLOCK, Siegfried ,  BOZENHARDT, Johannes ,  LEIGSNERING, Franz ,  PFATTEICHER, Werner ,  SCHEWE, Franz-Clemens

    IPC分类号： G06F12/06

    CPC分类号： G06F12/0661

    摘要： The proposal is for an arrangement with a plurality of plug points (SP1, ...) which are interconnected via a system bus (SYB) having data and control lines, address lines (AL1, ...) taken to connections of the plug points (SP1, ...), one of which is connected to a selector terminal (AN1, ...), and plug-in functional units (FE1, ...), at least one (FE1; FE3) of which has means for connecting the address lines (AL1, ...) to this unit and each of the remaining functional units (FE2; FE4) has means for connecting the unit to the selector terminal (AN1, ...) of the plug point. Units performing read and write functions can be fitted at any plug point in such an arrangement. The invention is applicable in store-programmable controls.

    ANORDNUNG MIT STECKBAREN FUNKTIONSEINHEITEN
    9.
    发明公开
    ANORDNUNG MIT STECKBAREN FUNKTIONSEINHEITEN 无效
    ANORDNUNG MIT STECKBAREN FUNKTION SEINHEITEN

    公开(公告)号：EP0670062A1

    公开(公告)日：1995-09-06

    申请号：EP93924525.0

    申请日：1993-11-18

    申请人： SIEMENS AKTIENGESELLSCHAFT

    发明人： ABERT, Michael ,  BLOCK, Siegfried ,  BOZENHARDT, Johannes ,  LEIGSNERING, Franz ,  PFATTEICHER, Werner ,  SCHEWE, Franz-Clemens

    IPC分类号： G06F12

    CPC分类号： G06F12/0661

    摘要： The proposal is for an arrangement with a plurality of plug points (SP1, ...) which are interconnected via a system bus (SYB) having data and control lines, address lines (AL1, ...) taken to connections of the plug points (SP1, ...), one of which is connected to a selector terminal (AN1, ...), and plug-in functional units (FE1, ...), at least one (FE1; FE3) of which has means for connecting the address lines (AL1, ...) to this unit and each of the remaining functional units (FE2; FE4) has means for connecting the unit to the selector terminal (AN1, ...) of the plug point. Units performing read and write functions can be fitted at any plug point in such an arrangement. The invention is applicable in store-programmable controls.

    摘要翻译： 该建议是针对具有多个插入点（SP1，...）的布置，所述插入点经由系统总线（SYB）互连，所述系统总线具有数据线和控制线，地址线（AL1，...） 其中一个连接到选择器端子（AN1，...）的点（SP1，...）和插入功能单元（FE1，...），其中至少一个（FE1; FE3） 具有用于将地址线（AL1，...）连接到该单元并且每个其余功能单元（FE2; FE4）具有用于将该单元连接到插头点的选择器端子（AN1，...） 。 执行读写功能的单元可以安装在任何插入点。 本发明适用于商店可编程控制。