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    ULTRA-COMPACT AND MICROPOWER CIRCUIT TO MONITOR PRROCESS, VOLTAGE, AND TEMPERATURE WITH HIGH ACCURACY
    2.
    发明公开
    ULTRA-COMPACT AND MICROPOWER CIRCUIT TO MONITOR PRROCESS, VOLTAGE, AND TEMPERATURE WITH HIGH ACCURACY 审中-公开

    公开(公告)号：EP4443177A1

    公开(公告)日：2024-10-09

    申请号：EP24166114.9

    申请日：2024-03-26

    申请人： Avago Technologies International Sales Pte. Limited

    发明人： Grassi, Alberto ,  Surana, Saurabh ,  Singh, Ullas ,  Kocaman, Namik

    IPC分类号： G01R31/28 ,  G01R31/30

    CPC分类号： G01R31/2882 ,  G01R31/30 ,  G01R31/2856

    摘要： A device includes a circuit that generates a first current associated with a voltage of a region of a semiconductor substrate, a second current associated with a temperature of the region, a third current associated with a first process parameter of the region, and a fourth current associated with a second process parameter of the region. A multiplexer of the device receives the first, second, third, and fourth currents and selects the currents one by one and periodically. A ring oscillator of the device is coupled to the multiplexer and receives the first, second, third, and fourth currents one by one and periodically, from the multiplexer. The ring oscillator oscillates at oscillation frequencies that are based on the received current from the multiplexer. The voltage, temperature, and the first and second process parameters of the region are determined based on the oscillation frequencies.

    SPLIT-DITHERING SCHEME IN SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER
    4.
    发明公开
    SPLIT-DITHERING SCHEME IN SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER 审中-公开

    公开(公告)号：EP4439986A1

    公开(公告)日：2024-10-02

    申请号：EP24166374.9

    申请日：2024-03-26

    申请人： Avago Technologies International Sales Pte. Limited

    发明人： Liu, Yong ,  Zhang, Wei ,  Cao, Jun

    IPC分类号： H03M1/06 ,  H03M1/46

    CPC分类号： H03M1/0641 ,  H03M1/46

    摘要： A system includes a dither generator module that includes a most significant bits (MSB) dither generator device that generates a first random value. The dither generator module also includes a least significant bits (LSB) dither generator device that generates a second random value. The system further includes a first digital to analog converter (DAC) that receives a sum of the first random value and the second random value and generates a dither signal based on the sum of the first random value and the second random value. The system also includes an analog to digital converter (ADC) that receives a sum of the dither signal and a sampled input signal and generates a first digitized signal. The system includes a subtraction module that subtracts the sum of the first random value and the second random value from the first digitized signal to produce a digitized output signal.

    SYSTEMS AND METHODS FOR ADDRESS SCRAMBLING
    8.
    发明公开
    SYSTEMS AND METHODS FOR ADDRESS SCRAMBLING 审中-公开

    公开(公告)号：EP4411552A1

    公开(公告)日：2024-08-07

    申请号：EP24154336.2

    申请日：2024-01-29

    申请人： Avago Technologies International Sales Pte. Limited

    发明人： Mitra, Bhaswar ,  Birman, Mark

    IPC分类号： G06F12/14

    CPC分类号： G06F12/1408 ,  G06F2212/105220130101

    摘要： A system including memory, a lookup circuit and an address circuit. The memory can store a plurality of tables. Each table can have a plurality of entries and each entry can have an entry index. The lookup circuit can be coupled with the memory. The lookup circuit can provide the plurality of entry indexes of the plurality of tables to the address circuit. The address circuit can include a first circuit, a second circuit, and third circuit. The first circuit can include a plurality of entry scramblers. The second circuit can include a plurality of translators, and the third circuit can include a plurality of row scramblers.

    LIGHT-WEIGHT MECHANISM FOR CHECKING MESSAGE INTEGRITY IN DATA PACKETS
    9.
    发明公开
    LIGHT-WEIGHT MECHANISM FOR CHECKING MESSAGE INTEGRITY IN DATA PACKETS 审中-实审

    公开(公告)号：EP4312402A3

    公开(公告)日：2024-08-07

    申请号：EP23209363.3

    申请日：2018-11-22

    申请人： Avago Technologies International Sales Pte. Limited

    发明人： Tzeng, Jeffrey ,  Choudhury, Abhijit K. ,  Kwentus, Alan Y.

    IPC分类号： H04L49/55 ,  H04L9/40

    CPC分类号： H04L63/123 ,  H04L63/0428 ,  H04L49/55 ,  H04L49/9057

    摘要： This disclosure presents a technique to include a packet sequence number and an integrity check value (ICV) into a data frame while maintaining a total number of transmitted bytes. A transmitting device includes circuitry that generates the ICV, inserts a transmitter packet sequence number into the data frame that includes a data packet including a payload, the data packet following a preamble and an interpacket gap (IPG) following the data packet. The circuitry also inserts the ICV into the data frame, and transmits the data frame, wherein inserting the ICV into the data frame reduces a size of the IPG while maintaining a total number of bytes in the data frame. A receiving device includes circuitry that receives the data frame, compares a receiver packet sequence number to the transmitter packet sequence number, and determines whether the transmitter packet sequence number is valid based on the receiver packet sequence number.