公开(公告)号：EP0140567A3

公开(公告)日：1987-08-05

申请号：EP84306429

申请日：1984-09-20

申请人： SONY CORPORATION

发明人： Kikuchi, Akihiro c/o Patent Division

IPC分类号： H03L07/10

CPC分类号： H03L7/10

摘要： In an automatic frequency control (AFC) circuit (10) of a video tape recorder, a charge pump circuit (13,14) is used to form a control signal for a voltage controlled oscillator (VCO) 5 included in the AFC circuit by phase-comparing (12) a horizontal synchronising signal (HSYNC) from a video signal with an output of the VCO 5. An AFC-identification circuit (24) can be added to the AFC circuit (10) to make locking-in of the circuit (10) smooth and fast when the AFC circuit is out of a lock-in range.

公开(公告)号：EP0184700A3

公开(公告)日：1988-06-01

申请号：EP85114817

申请日：1985-11-22

申请人： International Business Machines Corporation

发明人： Coburn, Ronald Leon

IPC分类号： H03L07/10

CPC分类号： H03L7/113

摘要： A circuit arrangement for recovering data from a communications network includes a Phase Lock Loop or PLL 10 with a voltage controlled oscillator or VCO 26 and a circuit 12 for automatically centering the VCO. The circuit arrangement 12 includes a counter that stores a changeable digital word. The digital word provides an adjustable current for driving the VCO. Initially, the VCO is driven so that its output signal falls within a predetermined frequency range. An error voltage representing the difference between a predetermined voltage range is developed and is used to change the contents of the counter until the VCO is centered. Thereafter the count that causes centering of the VCO is locked in the counter and normal PLL function is enabled.

公开(公告)号：EP0094837A3

公开(公告)日：1985-06-12

申请号：EP83302802

申请日：1983-05-17

申请人： WESTINGHOUSE ELECTRIC CORPORATION

发明人： Lee, Ronald Lloyd

IPC分类号： H03L07/10

CPC分类号： H03L7/10

摘要： A phase-locked loop having improved off-frequency detection. A variable frequency output signal (V sw ) is to be precisely locked to the frequency and phase of an alternating input signal. This is accomplished by alternately utilizing two feedback loops [Fig. 1 (V out , 14, 15)). A reference signal (V ref 1 ,), having a frequency approximately equal to the frequency of the input signal is input to an initialization feedback loop 14 in which it is mixed with the output signal. The Initialization loop produces a feedback signal for controlling a voltage controlled oscillator (12) which generates the output signal. An off-frequency detector (32) detects the frequency difference between the output signal and the reference signal. When this frequency difference decreases below a predetermined level, the off-frequency detector disables the initialization feedback loop and enables a primary feedback loop. In the primary feedback loop the phase of the output signal is compared (14) to the phase of the input signal, and the difference signal controls the voltage controlled oscillator in such a manner that the phase of the output signal tracks the phase of the input signal. With this scheme, the initialization loop, which has a wide bandwidth, is used to control the voltage controlled oscillator over a wide range of frequencies of the output signal (i.e., the initialization loop has a broad capture range). When the frequency of the output signal has been brought within the capture range of the primary loop, operation is switched to the primary loop. The primary loop has a narrower bandwidth and therefore provides better noise rejection than the Initialization loop.

公开(公告)号：EP0211594A3

公开(公告)日：1988-11-23

申请号：EP86305802

申请日：1986-07-29

申请人： Libera Developments Limited

发明人： Haine, John Leslie

IPC分类号： H03L07/18 ,  H03L07/10

CPC分类号： H03L7/187 ,  H03L7/1972

摘要： A phase-locked digital synthesiser comprises a voltage-­controlled oscillator (6) supplying a frequency divider (7) the output of which is fed to a phase-sensitive detector (9) also receiving an input from a reference oscillator (10). The output of the detector (9) is fed back by a feedback loop to the voltage-controlled oscillator (6) to achieve phase-locking. The divider (7) receives an input from a logic circuit (8) to control the division ratio of the divider (7), the logic circuit being prompted by a control signal which is also used to select one of a plurality of loop filters (12,13) connected for selectable use in the feedback loop from the detector (9) to the voltage controlled oscillator (6), the selected loop filter being appropriate to the prompted division ratio. Other embodiments include compensating means to correct a loop phase error arising from a change in the division ratio.

公开(公告)号：EP0085615A3

公开(公告)日：1986-03-19

申请号：EP83400185

申请日：1983-01-27

申请人： FUJITSU LIMITED

发明人： Okada, Toshiro

IPC分类号： H03L07/10

CPC分类号： H03L7/0893 ,  H03L7/107

摘要： A phase-locked loop circuit comprises a voltage-controlled oscillator, a phase comparator, a low-pass filter (15), a plurality of pump circuits (14S, 14F, ... ), and a selecting circuit (G 45 ) for selecting one of the pump circuits. The low-pass filter is comprised of a capacitor (C) and a plurality of resistors (R 1 , R 2 ) each connected to one of the pump circuits. By selecting one of the pump circuits to connect to a corresponding resistor, the cutoff frequency or time constant of the low-pass filter is switched in multi-steps.

公开(公告)号：EP0092657A3

公开(公告)日：1985-07-03

申请号：EP83101803

申请日：1983-02-24

申请人： Deutsche Thomson-Brandt GmbH

发明人： Maier, Gerhard ,  Selz, Alfred

IPC分类号： H03J05/02 ,  H03L07/10

CPC分类号： H03L7/107 ,  H03J5/0272

公开(公告)号：EP0092442A3

公开(公告)日：1985-02-20

申请号：EP83302255

申请日：1983-04-20

申请人： NEC CORPORATION

发明人： Ichiyoshi, Osamu c/o NEC Corporation

IPC分类号： H03L07/10

CPC分类号： H04L27/2272 ,  H03L7/10

摘要： A phase synchronizing circuit includes a voltage controlled oscillator (1) for generating an output signal in response to a control voltage, a phase comparator (2) for phase-comparing the output signal with a first signal to provide a second signal, a loop filter (3) for smoothing the second signal to provide the control voltage, a phase shifter (4) for phase-shifting the output signal by (π/2) + nπ(n being an integer) to a third signal, a first mixer (5) for mixing the third signal with an input signal to provide a fourth signal, a low-pass filter (6) for selecting a low frequency component from the fourth signal and providing a fifth signal whose phase is delayed in correspondance with the frequency difference between the input and the output signals and a second mixer (7) for mixing the fifth signal with the input signal to provide the first signal.

摘要翻译： 相位同步电路包括用于响应于控制电压产生输出信号的电压控制振荡器（1），用于将输出信号与第一信号进行相位比较以提供第二信号的相位比较器（2），环路滤波器 （3），用于平滑第二信号以提供控制电压;移相器（4），用于将输出信号相移（π/ 2）+nπ（n为整数）为第三信号;第一混频器 5），用于将第三信号与输入信号混合以提供第四信号;低通滤波器（6），用于从第四信号中选择低频分量，并提供相位与频率差相对应地延迟的第五信号 在输入和输出信号之间以及用于混合第五信号和输入信号以提供第一信号的第二混频器（7）。

公开(公告)号：EP0078084A3

公开(公告)日：1984-10-10

申请号：EP82201320

申请日：1982-10-22

申请人： Philips Patentverwaltung GmbH ,  N.V. Philips' Gloeilampenfabrieken

发明人： Kunze, Dieter ,  Onken, Gerd ,  Wölber, Jörg

IPC分类号： H03L07/10

CPC分类号： H03L7/107