公开(公告)号：EP4457693A1

公开(公告)日：2024-11-06

申请号：EP22917238.2

申请日：2022-12-22

申请人： Memcomputing, Inc.

发明人： TRAVERSA, Fabio Lorenzo

IPC分类号： G06N3/044 ,  G06N3/0442 ,  H03K19/20 ,  H03K19/21 ,  H03K19/17704 ,  G06N3/042 ,  G06N3/06 ,  G06N3/063 ,  G06N3/065 ,  G06N7/04 ,  H03K19/173

公开(公告)号：EP4133365A1

公开(公告)日：2023-02-15

申请号：EP21783872.1

申请日：2021-04-07

申请人： Rambus Inc.

发明人： VAN LOON, Marcel

IPC分类号： G06F7/58 ,  H03K19/21

公开(公告)号：EP4099571A1

公开(公告)日：2022-12-07

申请号：EP21177763.6

申请日：2021-06-04

申请人： Imec VZW

发明人： CIUBOTARU, Florin ,  ADELMANN, Hanns Christoph

IPC分类号： H03K19/168 ,  H03K19/21 ,  H03K19/23 ,  H03K19/18

摘要： A logic device based on spin waves, and comprising: a spin wave generator (110), a waveguide (120), at least two phase shifters (130), and an output port (140). The spin wave generator is connected with the waveguide (120) and is configured to emit a spin wave in the waveguide. The at least two phase shifters (130) are connected with the waveguide (120) at separate positions such that, when a spin wave is emitted by the spin wave generator, it passes via the phase shifters, wherein the at least two phase shifters are configured for changing a phase of the passing spin wave. The output port (140) is connected with the inline wave guide such that the at least two phase shifters (130) are present between the spin wave generator (110) and the output port (140).

公开(公告)号：EP4033666A1

公开(公告)日：2022-07-27

申请号：EP21216143.4

申请日：2019-01-28

申请人： Kandou Labs, S.A.

发明人： ULRICH, Roger ,  TAJALLI, Armin ,  HORMATI, Ali ,  SIMPSON, Richard

IPC分类号： H03K19/21 ,  H03L7/08 ,  H03L7/081 ,  H04L25/03 ,  H04B3/462 ,  H03L7/087 ,  H04L7/033 ,  H04L25/14 ,  H04L7/00

摘要： Methods and systems are described for receiving, over a plurality of consecutive signaling intervals, a plurality of codewords, each codeword received as a plurality of symbols via wires of a multi-wire bus, the plurality of symbols received at a plurality of multi-input comparators (MICs), wherein each symbol is received by at least two MICs, generating, for each codeword, a corresponding linear combination of the received symbols, generating a plurality of composite skew measurement signals over the plurality of consecutive signaling intervals, each composite skew measurement signal based on samples of one or more linear combinations, and updating wire-specific skew values of the wires of the multi-wire bus, wherein one or more wire-specific skew values are updated according to composite skew measurement signals associated with linear combinations formed by at least two different MICs.

公开(公告)号：EP3358747A2

公开(公告)日：2018-08-08

申请号：EP17179613.9

申请日：2010-04-19

申请人： Tela Innovations, Inc.

发明人： BECKER, Scott T.

IPC分类号： H03K19/21 ,  G06F17/50 ,  H03K19/20

CPC分类号： H03K19/20 ,  G06F17/5068 ,  H03K19/215

摘要： An exclusive-or circuit includes a pass gate controlled by a second input node. The pass gate is connected to pass through a version of a logic state present at a first input node to an output node when so controlled. A transmission gate is controlled by the first input node. The transmission gate is connected to pass through a version of the logic state present at the second input node to the output node when so controlled. Pullup logic is controlled by both the first and second input nodes. The pullup logic is connected to drive the output node low when both the first and second input nodes are high. An exclusive-nor circuit is defined similar to the exclusive-or circuit, except that the pullup logic is replaced by pulldown logic which is connected to drive the output node high when both the first and second input nodes are high.

公开(公告)号：EP3029839A4

公开(公告)日：2017-04-19

申请号：EP14831256

申请日：2014-06-09

申请人： MEISEI GAKUEN ,  BUFFALO MEMORY CO LTD

发明人： OTSUKA KANJI ,  SATO YOICHI ,  OKINAGA TAKAYUKI ,  AZUMA SHUICHIRO

IPC分类号： H03K19/21 ,  G06F1/02

CPC分类号： H03K19/21 ,  G06F1/02

摘要： To provide an arithmetic logic device that achieves arithmetic processing in a relatively short time on a relatively small circuit scale. [Solving Means] There is provided the logic operation device including a memory device 12 configured to store a lookup table and receive the input of a bit string N bits long, N being an integer of at least 2, the input bit string representing the address in the lookup table at which is stored multiple-bit data of which a part includes a bit representative of the result of a logical operation performed between the bits included in the input bit string. The memory device 12 is accessed so as to output the bits included in the data stored at the address represented by the received bit string.

公开(公告)号：EP2709277A1

公开(公告)日：2014-03-19

申请号：EP13354033.6

申请日：2013-09-13

申请人： Tiempo

发明人： Renaudin, Marc ,  Fonkoua, Alain ,  Monnet, Yanick ,  Rijmati, Yassine

IPC分类号： H03K19/21 ,  G06F9/38

CPC分类号： G06F13/4022 ,  G06F13/42 ,  H03K19/21

摘要： Le circuit asynchrone comporte un canal d'entrée (A), un opérateur de divergence (20) connectant le canal d'entrée à une pluralité de canaux intermédiaires (01, 02), un opérateur de convergence (22) regroupant les canaux intermédiaires en un seul canal de sortie (Z), un séquenceur principal (SEQ) comprenant une pluralité de canaux de commande (S1 ; S2) activés séquentiellement, chaque canal intermédiaire étant couplé à un canal de commande, et un interrupteur (C2) disposé dans le chemin de requête de l'un des canaux intermédiaires et connecté au canal de commande (S2) activé en dernier. Le circuit comporte en outre un circuit de mémorisation (MEM), disposé dans chacun des autres canaux intermédiaires (O1), connecté au canal de commande associé (S1) et configuré pour transmettre le signal de requête du canal intermédiaire associé vers le canal de sortie et pour modifier l'état en sortie du canal intermédiaire associé, au moyen du séquenceur principal, sans que le canal d'entrée (A) ne change d'état.

摘要翻译： 电路具有将输入通道连接到中间通道（O1，O2）的分支运算器（20）和收集输出通道（Z）中的中间通道的收敛运算器（22）。 主定序器（SEQ）包括顺序激活的控制信道（S1，S2）。 存储器电路（MEM）连接到相关联的控制信道，以将请求信号从相关联的中间信道发送到输出信道，并且由主定序器修改相关联的中间信道的输出状态，而不需要任何状态 更改输入通道。

公开(公告)号：EP2637310A1

公开(公告)日：2013-09-11

申请号：EP13354010.4

申请日：2013-03-06

申请人： Tiempo

发明人： Renaudin, Marc ,  Nguyen van Mau, David

IPC分类号： H03K19/21 ,  G06F9/38

CPC分类号： H03K19/17764 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/21

摘要： Le circuit asynchrone comprend une fourche (F) à au moins deux branches (B0, B1), chaque branche étant connectée à une porte logique (G0, G1) de sorte que la porte logique reçoive en entrée un signal de fin de branche (X0, X1). Il comporte en outre un circuit de dérivation (2a, 2b) du signal de fin de branche au niveau de chaque porte logique pour former un signal dérivé (X0', X1'), et un circuit de blocage comprenant une porte de Muller (C) et recevant en entrée au moins un signal dérivé, le circuit de blocage étant configuré pour empêcher la propagation d'un signal de sortie (Eack) lorsque les signaux de fin de branche (X0, X1) sont dans des états logiques différents.

摘要翻译： 该电路具有两个分支（B0，B1）的叉（F），其中每个分支连接到逻辑门，使得逻辑门从输入端的端子（X0，X1）接收分支结束信号。 导出电路（2a，2b）在每个逻辑门导出分支结束信号，以形成导出信号（X0'，X1'）。 阻塞电路包括调色门（G0，G1），并在输入端接收导出信号。 阻塞电路被配置为当分支结束信号处于不同的逻辑状态时，防止数据输出信号（S0，S1）和确认信号（Eack）的传播。 还包括用于降低对异步电路的延迟的灵敏度的方法的独立权利要求。

公开(公告)号：EP1668777A1

公开(公告)日：2006-06-14

申请号：EP04769381.7

申请日：2004-09-10

申请人： Koninklijke Philips Electronics N.V.

发明人： GUIRAUD, Lionel

IPC分类号： H03K19/086 ,  H03K19/21 ,  H03K3/2885

CPC分类号： H03K3/2885 ,  H03K19/086 ,  H03K19/212

摘要： The invention relates to an electronic circuit comprising differential signal input means, a combining stage, a discriminating stage and differential signal output means. The discriminating stage comprises four transistors (Q8, Q9, Q10, Q11) each having first electrodes (83, 93, 103, 113) and second electrodes (81, 91, 101, 111) and a respective gate electrode (82, 92, 102, 112). The first electrodes of said four transistors are connected to a common node. The combining stage is arranged to convert differential input signals into gate signals applied to the gate electrodes of some of said four transistors respectively.

公开(公告)号：EP1642388A1

公开(公告)日：2006-04-05

申请号：EP04767593.9

申请日：2004-07-06

申请人： ATMEL NANTES SA

发明人： COLOMA, Bernard

IPC分类号： H03K19/21

CPC分类号： G06F7/026 ,  H03K19/215

摘要： The invention relates to a device for comparing two words, N and P, of n bits each. The inventive device consists of at least one comparator block comprising n basic comparator blocks which can each be used to compare bits Ni and Pi of digit place i of words N and P, whereby 0 = i = n-1. Moreover, each basic comparator block comprises: a first sub-block which can be used to generate a first signal indicating whether or not bits Ni and Pi are equal, said signal being generated at the output of the sub-block forming a first output (OUT_XORi) of the basic comparator block; a second sub-block which can be used to generate a second signal indicating which of bits Ni and Pi is greater, said signal being generated at the output of the second sub-block; and a third sub-block which enables the second signal to pass to a second output (SOUTi) of the basic comparator block if the first signal indicates that bits Ni and Pi are not equal and which, in the opposite case, enables the second signal to be blocked. The comparator block also comprises: means for generating a third signal at a first output (OUT_XOR4_b) of the comparator block, indicating that numbers N and P are equal if the n first signals indicate same; and first selective passage means which can be used selectively to connect the second output (SOUTi) of a basic comparator block to a second output (OUT_COMP4) of the comparator block, whereby said basic comparator block, from among the basic comparator blocks having a second signal at the output thereof, processes the most significant bits. According to the invention, the signal present at the second output of the comparator block indicates which of the numbers, N or P, is greater.

摘要翻译： 本发明涉及一种用于比较每个n位的两个字N和P的装置。 本发明的装置由至少一个比较器块组成，该比较器块包括n个基本比较器块，每个比较器块可以用于比较字N和P的数字位i的比特Ni和Pi，从而0 = i = n-1。 此外，每个基本比较器块包括：第一子块，其可以用于生成指示比特Ni和Pi是否相等的第一信号，所述信号在子块的输出处生成，形成第一输出（ OUT_XORi）的基本比较器块; 第二子块，其可用于生成第二信号，所述第二信号指示比特Ni和Pi中的哪一个较大，所述信号在第二子块的输出处生成; 以及第三子块，如果第一信号指示比特Ni和Pi不相等并且在相反的情况下启用第二信号则使第二信号传递到基本比较器块的第二输出（SOUTi） 被阻止。 比较器块还包括：用于在比较器块的第一输出（OUT_XOR4_b）处产生第三信号的装置，指示如果n个第一信号指示相同，则数字N和P相等; 以及第一选择性通过装置，其可以有选择地用于将基本比较器块的第二输出（SOUTi）连接到比较器块的第二输出（OUT_COMP4），由此所述基本比较器块中的基本比较器块具有第二 信号在其输出端处理最高有效位。 根据本发明，存在于比较器块的第二输出处的信号指示N或P中的哪一个更大。