摘要:
A content addressable memory system includes an array of memory cells arranged in rows and columns in an array of N bit cells by M words, with N bits per word, an I/O bus having a bit capacity S which is a submultiple of N, a mode generator for generating a plurality of commands, the commands including a command write command, a data write command, a data read command, and a status read command, the command write and the status read commands being encodable in S bits or less, and multiplexing means for supplying selected ones of the commands to the I/O bus.
摘要:
A content addressable memory includes a memory array having a plurality of entries. Control circuitry is provided for sequentially presenting each entry in the array to a comparator. An input signal is also provided to the comparator. Entries matching the input signal are identified for later use. The input signal can be masked, so that only selected fields of each entry are compared to it. Conventional RAM technology can be used for the memory array. In the alternative, a serial memory array, such as an array formed from a charge coupled device, can be used.
摘要:
A plurality of memory units (114), called "mnemonds", is each capable of storing data elements and of responding to requests to recover those data elements from storage. A plurality of mnemonds is arranged in a linear array (112), with each mnemond connected to be capable of responding to signals from its neighbor mnemonds. When a data structure is stored, each array stores a copy of that data structure, either allocating the elements of the data structure one per mnemond (with possible wrap-around to the beginning of the linear array) or allocating the data structures to one or a predetermined number of mnemonds. When a data structure is to be located in memory through cueing precise correspondences between data stored and cueing data entered identify the unique location or locations of said matching data; when a data structure is to be recovered from memory identification of its location permits recovery of data in that location or in that location and succeeding locations. One or more arrays, of differing lengths so that the allocation of data elements is also differing, is collected to form a memory bank. One or more memory banks operates under the control of a central control unit.
摘要:
A content-addresable memory device for searching the address of an input data is disclosed. The content-addressable memory device comprises:
memory means including a matrix of memory cells including a plurality of pairs of columns, the row position of each of the memory cells corresponding to the content of the data, the position of each of the pairs of columns corresponding to the address, the first column of each pair of columns being for storing the data at the exact address and the second column of each pair of columns being for storing the data close to the data stored in the first column of the same pair of columns; row selecting means coupled to said memory means and for selecting a row of the memory cell matrix of said memory means corresponding to the input data to be searched. The content-addressable memory device may further comprise: column selecting means for, in response to an input data to be stored in an input address, selecting a pair of columns of the matrix of said memory means corresponding to said input address; and data writing means for writing the input data to be stored in the first column of the pair of columns of said matrix selected by the column selecting means and the data associated to said input data in the second column of the pair of columns selected by the column selecting means, whereby it is possible to store data and it's associated data in the same address so as to carry out search of the associated data at a high execution speed.
摘要:
The memory system includes a plurality of reconfigurable subarrays of memory cells (SUBO...SUB3) and having the capability of simultaneously performing write/compare, read/compare, compare/bypass, write/bypass, or write/ compare/bypass operations. The present system may be fabricated on a single integrated circuit chip and includes circuitry for selectively writing data into the subarrays (12, WD10...WD18, BDO...BD3, WSO...WS3). Output data from the subarrays (SUBO...SUB3) is connected to compare data logic (CL10...CL13, CL20...CL23) for comparing the subarray data to one or more bytes of compare input data, and to bit select logic (BSO...BS3) for selectively placing the subarray data onto an output bus. Bypass select logic (24) causes either the subarray data or one byte of compare data to be output from the memory system data output port. In one embodiment, two bytes of compare input data can be simultaneously compared with a selected data byte from each of the subarrays (SUBO...SUB3), and one byte of compare input data can be bypassed to the data output port during the compare operation. Additionally, data may be written into the subarrays (SUBO...SUB3) while simultaneously performing the compare or the compare/bypass operations.
摘要:
57 A method is provided for searching an association matrix using associative searching techniques. The method contemplates the use of two types of data structures. Firstly, a data structure for locating a particular instance or component in a matrix. Secondly, an associative matrix representing the relationship of the components or instances to one another. The search method requires searching the first data structure to determine the position of the component in the association matrix. The appropriate portion of the matrix is then addressed and horizontal and vertical masks are established for manipulation of the data in the matrix using an associative array processor. Utilising the masks the association matrix may be traversed both vertically and horizontally to identify the desired relationships. The method uniquely takes advantage of the architecture of an associative array processor to provide for the simultaneous searching of rows or columns in response to a single instruction. Thus, the method significantly reduces the search time making the use of association matrices practical along with the reduced storage requirements of such matrices.