公开(公告)号：EP1551004A2

公开(公告)日：2005-07-06

申请号：EP05006584.6

申请日：2003-01-28

申请人： SEIKO EPSON CORPORATION

发明人： Morita, Akira

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G3/2011 ,  G09G3/32 ,  G09G3/3233 ,  G09G3/325 ,  G09G3/3614 ,  G09G3/3685 ,  G09G3/3696 ,  G09G5/06 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2310/0248 ,  G09G2310/0251 ,  G09G2310/027 ,  G09G2310/04 ,  G09G2320/0276

摘要： A reference voltage generation circuit that generates multi-valued reference voltages for driving a liquid crystal display comprises: first to fourth ladder resistor circuit (312, 322, 332, 342) between first and second power source lines. First to i-th reference voltage output switching circuits (VSW1-VSWi) are respectively inserted between first to i-th division nodes (ND 1 -ND i ) of the first ladder resistor circuit (312), where i is an integer larger than or equal to 2, and first to i-th reference voltage output nodes (VND 1 -VND i ). (i + 1)th to 2i-th reference voltage output switching circuits (VSW(i+1)-VSW2i) are respectively inserted between (i + 1)th to 2i-th division nodes (ND i+1 -ND 2i ) of the second ladder resistor circuit (322) and the first to i-th reference voltage output nodes. (2i + 1)th to 3i-th reference voltage output switching circuits (VSW(2i+1)-VSW(3i)) are respectively inserted between (2i + 1)th to 3i-th division nodes (ND 2i+1 -ND 3i ) of the third ladder resistor circuit (332) and the first to i-th reference voltage output nodes. (3i + 1)th to 4i-th reference voltage output switching circuits (VSW(3i+1)-VSW(4i)) are respectively inserted between (3i + 1)th to 4i-th division nodes (ND 3i+1 -ND 4i ) of the fourth ladder resistor circuit (342) and the first to i-th reference voltage output nodes. When polarity inversion of a voltage outputted by a polarity inversion drive system to a signal electrode at a given polarity inversion period is repeated: the first to i-th reference voltage output switching circuits are switched on during a given control period in a positive polarity driving period and switched off during a given control period in a negative polarity driving period; the (i + 1)th to 2i-th reference voltage output switching circuits are switched off during a given control period in the positive polarity driving period and switched on during a given control period in the negative polarity driving period; the (2i + 1)th to 3i-th reference voltage output switching circuits are switched on during the positive polarity driving period and switched off during the negative polarity driving period; and the (3i + 1)th to 4i-th reference voltage output switching circuits are switched on during the positive polarity driving period and switched off during the negative polarity driving period.

摘要翻译： 产生用于驱动液晶显示器的多值参考电压的参考电压产生电路包括：在第一和第二电源线之间的第一至第四梯形电阻电路（312,322,332,342）。 第一到第i参考电压输出切换电路（VSW1-VSWi）分别插入在第一梯形电阻电路（312）的第一到第i分割节点（ND1-NDi）之间，其中i是大于或等于 到2，并且第一到第i参考电压输出节点（VND1-VNDi）。 在第（i + 1）到第2i个分割节点（NDi + 1-ND2i）之间分别插入第（i + 1）到第2i个参考电压输出切换电路（VSW（i + 1）-VSW2i） 第二梯度电阻器电路（322）和第一至第i参考电压输出节点。 （2i + 1）至第3i分割节点（ND2i + 1-ND3i）之间分别插入第2i + 1至第3i参考电压输出切换电路（VSi（2i + 1） ）的第三梯形电阻器电路（332）和第一至第i参考电压输出节点。 在第（3i + 1）至第4i分割节点（ND3i + 1-ND4i）之间分别插入第（3i + 1）至第4i参考电压输出切换电路（VSW（3i + 1）-VSW（4i） ）的第四梯形电阻器电路（342）和第一至第i参考电压输出节点。 当重复由极性反转驱动系统输出到给定极性反转周期中的信号电极的极性反转时：第一至第i参考电压输出开关电路在正极性驱动的给定控制周期期间接通 并且在给定的控制周期期间在负极性驱动周期期间断开; 第（i + 1）至第2i参考电压输出开关电路在正极性驱动时段的给定控制时段期间被关断并且在负极性驱动时段的给定控制时段期间被开启; （2i + 1）至第3i参考电压输出开关电路在正极性驱动时段期间接通并且在负极性驱动时段期间断开; 和第（3i + 1）至第4i参考电压输出开关电路在正极性驱动时段期间接通并且在负极性驱动时段期间断开。

公开(公告)号：EP1543490A1

公开(公告)日：2005-06-22

申请号：EP03797458.1

申请日：2003-09-12

申请人： Koninklijke Philips Electronics N.V.

发明人： DEAN, John, E.

IPC分类号： G09G3/34 ,  G09G3/36 ,  H04N9/31

CPC分类号： G09G3/342 ,  G09G3/2025 ,  G09G3/2077 ,  G09G3/3611 ,  G09G2310/0235 ,  G09G2310/024 ,  G09G2310/027 ,  G09G2310/0297 ,  G09G2320/0633 ,  H04N9/3117

摘要： A method of increasing image dynamic range by breaking each pixel into two or more time displaced samples that are presented to the display in synchronization with appropriate illumination.

公开(公告)号：EP1280126A4

公开(公告)日：2005-06-08

申请号：EP01949055

申请日：2001-02-05

申请人： NICHIA CORP

发明人： NAGAI YOSHIFUMI ,  TSUJIMOTO HIROSHI ,  NAKANO YOSHIYUKI ,  TSUJI RYUHEI

IPC分类号： H04N9/30 ,  G09G1/28 ,  G09G3/20 ,  G09G3/32 ,  G09G5/02 ,  H04N9/64

CPC分类号： G09G3/2077 ,  G09G1/285 ,  G09G3/2003 ,  G09G3/2014 ,  G09G3/32 ,  G09G3/3283 ,  G09G5/02 ,  G09G2300/06 ,  G09G2310/027 ,  G09G2310/0272 ,  G09G2320/02 ,  G09G2320/0285 ,  G09G2320/0666 ,  G09G2340/06 ,  G09G2360/145

摘要： An image display exhibiting high reproducibility by correcting variation in the chromaticity of light emitting elements and thereby uniforming the color tone of pixels, and a control method thereof. The image display comprises a display section (10) where light emitting elements of a plurality of color tones are arranged for each pixel, a drive section (50) for supplying the light emitting elements of each pixel with a drive current according to image data concerning the color tones, and a chromaticity correcting section (11) for distributing a specified part of drive current, supplied from the drive section (50) to a light emitting element corresponding to at least one of the color tones of each pixel, to a light emitting element corresponding to one or more other color tone of the pixel.

公开(公告)号：EP1530743A1

公开(公告)日：2005-05-18

申请号：EP03771463.1

申请日：2003-03-17

申请人： Samsung Electronics Co., Ltd.

发明人： MOH, Sang-Moon

IPC分类号： G02F1/133

CPC分类号： G09G3/3688 ,  G09G3/3614 ,  G09G3/3648 ,  G09G2310/0248 ,  G09G2310/027 ,  G09G2310/063 ,  G09G2310/065 ,  G09G2320/0233 ,  G09G2330/023

摘要： The present invention relates to a liquid crystal display with multi-line inversion which reverses polarity of applied voltages every two or more rows for preventing the deterioration of liquid crystal. An LCD according to the present invention includes a LC panel in matrix arrangement, a timing controller performing data format of image data from an external graphics source, a voltage generator generating voltages for driving the LC panel, a gate driver sequentially scanning gate lines of the LC panel by unit of one horizontal scanning period, and a data driver outputting analog gray voltages selected based on the image data to the data lines of the LC panel. The data driver includes a data line bias circuit biasing the data lines to an intermediate level voltage whenever displaying the pixels in one row. Accordingly, the amount of stored charges between the pixels in the rows with polarity inversion and the pixels in the rows without polarity inversion is reduced, and consequently, the luminance difference between the pixels in the rows with the polarity inversion. In addition, the present invention elongates the application duration of the data signals for pixels in the rows with the polarity inversion compared with the application duration of the data signals for the pixels in the rows with the polarity inversion compared with the application duration of the data signals for the pixels in the rows without the polarity inversion such that the difference in the charge storage between the two rows is reduced.

公开(公告)号：EP1509899A2

公开(公告)日：2005-03-02

申请号：EP03736118.5

申请日：2003-06-09

申请人： Casio Computer Co., Ltd.

发明人： YAMADA, Hiroyasu ,  TAKEI, Manabu

IPC分类号： G09G3/32

CPC分类号： G09G3/325 ,  G09G2300/0417 ,  G09G2300/0819 ,  G09G2300/0847 ,  G09G2300/0852 ,  G09G2300/0866 ,  G09G2310/027 ,  G09G2320/0223 ,  G09G2320/043

摘要： A display panel (110) comprises a plurality of optical elements (OEL) each having a pair of electrodes and performing an optical operation according to current passing between the pair of electrodes, a current line (DL), a switch circuit (Tr2) that passes a write current (Ia) with a predetermined current value through the current line (DL) during a selection time (Tse) and stops passing current during a non-selection time (Tnse), and a current storage circuit (Trl, Tr2, Cs, Cp) that stores current data according to the current value of the write current (Ia) passing through the current line (DL) during the selection time (Tse) and that supplies a drive current (Ib) having a current value, which is obtained by subtracting a predetermined offset current (Ioff) from the current value of the stored write current (Ia), to the optical elements (OEL) during the non-selection time (Tnse). The current storage circuit (Trl, Tr2, Cs, Cp) includes a first capacitor device (Cs) to which an electrical charge corresponding to the write current (Ia) is written and a second capacitor device (Cp) to which an electrical charge corresponding to offset current (Ioff) is written, and the second capacitor device (Cp) has a capacitive value, which is equal to or larger than the first capacitor device (Cs).

公开(公告)号：EP1494202A1

公开(公告)日：2005-01-05

申请号：EP03715474.7

申请日：2003-03-27

申请人： SANYO ELECTRIC CO., LTD. ,  Sanyo Telecommunications Co., Ltd. ,  Mori, Yukio ,  Tanase, Susumu ,  Yamashita, Atsuhiro ,  Inoue, Masutaka ,  Kinoshita, Shigeo ,  Murata, Haruhiko ,  Yabukawa, Takashi ,  Goya, Hiroyuki

发明人： MORI, Yukio ,  TANASE, Susumu ,  YAMASHITA, Atsuhiro ,  INOUE, Masutaka ,  KINOSHITA, Shigeo ,  MURATA, Haruhiko ,  YABUKAWA, Takashi ,  GOYA, Hiroyuki

IPC分类号： G09G3/30 ,  G09G3/20 ,  H05B33/14

CPC分类号： G09G3/20 ,  G09G3/3275 ,  G09G2300/0809 ,  G09G2300/0842 ,  G09G2310/027 ,  G09G2320/0626 ,  G09G2330/022 ,  G09G2330/028 ,  G09G2330/04 ,  G09G2360/144

摘要： When an input detection unit (64) has detected that no user operation has been performed to an organic EL display apparatus (11) for a predetermined period of time or when a processing detection unit (66) has detected that a predetermined processing is being performed, the input detection unit (64) or the processing detection unit (66) outputs an instruction to a reference voltage adjusting unit (72) to modify a reference voltage referenced by a DAC unit (42) upon conversion to an analog output signal.

公开(公告)号：EP1469449A1

公开(公告)日：2004-10-20

申请号：EP03758866.2

申请日：2003-10-24

申请人： Sony Corporation

发明人： TAMURA, Mitsuyasu, c/o SONY CORPORATION ,  HASEGAWA, Hiroshi, c/o SONY CORPORATION

IPC分类号： G09G3/30 ,  G09G3/20 ,  H05B33/12 ,  H05B33/14

CPC分类号： G09G3/2092 ,  G09G3/3233 ,  G09G3/3241 ,  G09G2300/0842 ,  G09G2310/0251 ,  G09G2310/0262 ,  G09G2310/027 ,  G09G2320/0242 ,  G09G2320/0261 ,  G09G2320/0276 ,  G09G2320/029 ,  G09G2320/043 ,  G09G2320/045 ,  G09G2320/048 ,  G09G2320/0626 ,  G09G2320/066 ,  G09G2320/0666 ,  G09G2320/103 ,  G09G2330/021 ,  G09G2330/028 ,  G09G2360/144 ,  G09G2360/16

摘要： A circuit for generating drive signals (SHR, SHG and SHB) from an input image signal (SIN), a cell array (1) including a light emitting element (EL) for emitting light of a predetermined color of red (R), green (G) or blue (B) by being applied with a drive signal (SHR, SHG and SHB) supplied for each color from the circuit (2), an adjustment information retrieve means (4) for obtaining information relating light emission adjustment of the light emitting element (EL), and a level adjustment circuit (2B) provided in the circuit (2) for changing a level of an RGB signal (S22) before divided to drive signals (SHR, SHG and SHB) for the respective RGB colors based on the information obtained by the adjustment information retrieve means (4) are provided. In the present invention, color balance adjustment can be performed by the above small scale circuit.

摘要翻译： 一种用于从输入图像信号（SIN）产生驱动信号（SHR，SHG和SHB）的电路，包括用于发射预定颜色的红色（R）的光的发光元件（EL）的单元阵列（1），绿色 （2）的每个颜色提供的驱动信号（SHR，SHG和SHB），提供调整信息检索装置（4），用于获得关于（G）或蓝色（B）的发光调整 发光元件（EL）以及设置在电路（2）中的电平调节电路（2B），用于改变RGB信号（S22）的电平，然后被分成各个RGB颜色的驱动信号（SHR，SHG和SHB） 基于由调节信息检索装置（4）获得的信息。 在本发明中，可以通过上述小规模电路进行色彩平衡调节。

公开(公告)号：EP1459287A1

公开(公告)日：2004-09-22

申请号：EP02785826.5

申请日：2002-12-03

申请人： Koninklijke Philips Electronics N.V.

发明人： HECTOR, Jason, R. ,  KNAPP, Alan, G.

IPC分类号： G09G3/36

CPC分类号： G09G3/2011 ,  G09G3/3688 ,  G09G3/3696 ,  G09G2310/027 ,  G09G2310/06 ,  G09G2330/021

摘要： A liquid crystal display has a plurality of buffers 46 controlling a plurality of column lines. The buffers have a bias current control input 47 which is controlled, in the example by timing circuitry 50, to set the current during the row period for writing to each row of pixels. In particular, the row period may be divided between a drive period with a high buffer bias current and a voltage maintenance period with a lower buffer bias current.

公开(公告)号：EP1450342A1

公开(公告)日：2004-08-25

申请号：EP02775426.6

申请日：2002-10-30

申请人： SEL SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

发明人： KIMURA, Hajime, SEMICONDUCTOR ENERGY LAB. CO., LTD

IPC分类号： G09G3/30 ,  G09G3/20 ,  H05B33/14

CPC分类号： G09G3/3283 ,  G09G3/2022 ,  G09G3/2077 ,  G09G3/3241 ,  G09G3/325 ,  G09G3/3266 ,  G09G3/3291 ,  G09G2300/0426 ,  G09G2300/0842 ,  G09G2300/0852 ,  G09G2300/0861 ,  G09G2310/0216 ,  G09G2310/0262 ,  G09G2310/027

摘要： Variation occurs in transistor characteristics. The present invention relates to a signal line driver circuit comprising a plurality of current source circuits respectively corresponding to a plurality of wirings, characterized in that: the plurality of current source circuits each comprise capacitor means and supply means; and the plurality of current source circuits each convert a supplied current into a voltage in accordance with a video signal, and supply a current corresponding to the converted voltage.

摘要翻译： 变形例的发生在晶体管特性。 本发明涉及一种信号线驱动电路，包括电流源电路分别对应于布线的复数，在该特点的多元性：电流源电路的每个包括电容器装置，以及供给的多元性; 和电流源电路的多元性每个转换的电流成雅舞蹈提供与视频信号的电压，并提供一个相应的电流转换后的电压。

公开(公告)号：EP1447787A1

公开(公告)日：2004-08-18

申请号：EP02775427.4

申请日：2002-10-30

申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

发明人： KIMURA Hajime, c/o SEMICONDUCTOR ENERGY LAB CO LTD

IPC分类号： G09G3/30 ,  G09G3/20 ,  H05B33/14

CPC分类号： G09G3/325 ,  G09G3/2022 ,  G09G3/3241 ,  G09G3/3283 ,  G09G2300/0426 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2310/027 ,  G09G2320/043

摘要： The variation of characteristics of transistors occurs. The present invention is a signal line drive circuit having a plurality of current source circuit corresponding to a plurality of wirings, a first and a second shift registers, a latch circuit, the foregoing plurality of current source circuits have capacity means and supplying means, respectively, characterized in that the foregoing capacity means converts a supplied current into a voltage according to a sampling pulse supplied from the foregoing first shift register, the foregoing supplying means supplies a current corresponding to the foregoing converted voltage according to a video signal, and the foregoing latch circuit operates according to a sampling pulse supplied from the foregoing second shift register.

摘要翻译： 晶体管的特性发生变化。 本发明是一种信号线驱动电路，具有对应于多个布线的多个电流源电路，第一和第二移位寄存器，锁存电路，上述多个电流源电路分别具有容量装置和供电装置 其特征在于，上述电容装置根据从上述第一移位寄存器提供的采样脉冲将供电电流转换为电压，上述供电装置根据视频信号提供与上述转换电压相对应的电流，上述 锁存电路根据从上述第二移位寄存器提供的采样脉冲进行工作。