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公开(公告)号:EP0423988A3
公开(公告)日:1993-04-21
申请号:EP90310918.9
申请日:1990-10-04
发明人: Epstein, Howard C.
CPC分类号: H03M1/0678 , G01D5/366 , H03M1/308
摘要: A shaft angle encoder is provided with a symmetrical code wheel and pattern of photodetectors for providing an index pulse indicative of shaft angular position. The code wheel has two concentric index tracks each of which is symmetrical in a circumferential direction and are symmetrical with respect to each other and also with respect to a data track for indicating increments of angular position. In an exemplary embodiment there is a pair of windows of unit width in the one index track with a spoke therebetween with a width of at least two units. A pair of lateral windows extend away from each other more than a unit width along the second track. An opaque area at least two units wide is provided between the lateral windows in the second track. The photodetectors are arranged so that when the code wheel is in the index pulse position, a pair of photodetectors for the inner track are illuminated through the windows in the inner track, and two photodetectors for the outer track are both occulted by the opaque area between the lateral windows in the second track. Such an arrangement provides symmetry of the code wheel so that it can be inverted either accidentally or intentionally during assembly and yet side lobes of photocurrent from the photodetectors on the separate tracks are not coincident, thereby avoiding false index pulse triggers.
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公开(公告)号:EP0393728B1
公开(公告)日:1993-04-07
申请号:EP90110749.0
申请日:1986-09-09
IPC分类号: H03M1/66
CPC分类号: H03M1/0872 , H03K5/023 , H03K17/6871 , H03K17/693 , H03K19/018564 , H03M1/0678 , H03M1/745
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公开(公告)号:EP0376538A3
公开(公告)日:1992-10-21
申请号:EP89312949.4
申请日:1989-12-12
CPC分类号: G01D5/249 , G01D5/24438 , H03M1/0678 , H03M1/301
摘要: An optical shaft angle encoder has a plurality of active photodiodes (26) in an array on a semiconductor chip. A rotating code wheel (3) has alternating areas (13, 15) for alternately illuminating or not illuminating the active photodiodes (26) in response to the rotation of the wheel (3). Errors in the duty cycle involving the end active photodiodes (26) in the array are largely avoided by having a plurality of inactive photodiodes (27) at each end of the array with width and electrical properties effectively the same as the active photodiodes (26) so that leakage current to each end active photodiode (26) of the array is substantially equal to the leakage current to active photodiodes (26) remote from the end of the array. Similarly, leakage current which may affect the duty cycle of individual photodiodes (26) may be minimized by surrounding the individual photodiodes with a reverse biased photodiode junction.
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公开(公告)号:EP0477293A1
公开(公告)日:1992-04-01
申请号:EP90910639.0
申请日:1990-06-11
IPC分类号: H03M1
CPC分类号: H03M1/0678 , H03M1/785
摘要: Un convertisseur numérique/analogique de multiplication comprend des pattes de dérivation, dans lesquelles un commutateur (15) comporte une borne commune connectée à un noeud respectif (12) dans le chemin en série ainsi que deux bornes commutables connectées chacune à une résistance respective. Chaque branche de la série se compose d'un commutateur fictif (28) en série avec une résistance intercalée (13) ayant la moitié de la valeur de résistance de chacune des résistances de dérivation (14', 14''). Les commutateurs, mis en oeuvre de préférence en technologie MOS complémentaire sont physiquement appareillés et les commutateurs se trouvant dans les branches sont configurés pour être fermés, de sorte que la résistance de chaque commutateur fictif représente la moitié de celle du commutateur se trouvant dans la patte de dérivation respective. L'agencement permet de conserver la relation R-2R entre la série et les résistances de dérivation, et améliore ainsi sensiblement la linéarité dudit convertisseur.
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95.
公开(公告)号:EP0186239B1
公开(公告)日:1991-03-20
申请号:EP85202045.2
申请日:1985-12-11
IPC分类号: H01L27/10
CPC分类号: H01L27/101 , H03M1/0678 , H03M1/804 , Y10S257/925
摘要: An integrated circuit includes capacitances of different capacitance values, this circuit having rows of basic capacitances, while the capacitances have different numbers of basic capacitances connected in parallel between a first connection electrode and an associated second connection electrode. Plural rows have the same number of n basic capacitances and in different ones of these rows different numbers of basic capacitances form part of the capacitances, all the remaining basic capacitances of the relevant rows being dummy capacitances. The second capacitance electrodes are connected to one or more further connection electrodes.
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公开(公告)号:EP0222999A3
公开(公告)日:1989-12-13
申请号:EP86112443.6
申请日:1986-09-09
CPC分类号: H03M1/0872 , H03K5/023 , H03K17/6871 , H03K17/693 , H03K19/018564 , H03M1/0678 , H03M1/745
摘要: A high speed monolithic current switching digital-to-analog converter (DAC) having a sampled output is provided. The DAC (10) includes an output sampling circuit (9) which is an on/off switch rather than a sample and hold circuit. Elimination of a holding capacitor results in faster switching and less error. The sampler (9) is a differential, triple balanced architecture which steers the DAC's differential outputs alternately to a load resistor via a balancing transformer (11) and to ground. The sampler (9) includes a three-stage, AC coupled GaAs pre- amp (15) which provides a complementary clock to drive the sampler.
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