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公开(公告)号：EP3280054A3
公开(公告)日：2018-08-08
申请号：EP17163286.2
申请日：2017-03-28
申请人： NXP USA, Inc.
CPC分类号： H03M1/1042 , H03M1/0678 , H03M1/1004 , H03M1/12 , H03M1/121 , H03M1/123 , H03M1/60
摘要： The embodiments described herein provide analog-to-digital converters (ADCs) and systems and methods for calibrating ADCs, including ADCs with poorly characterized nonlinearities that cannot be effectively calibrated with traditional calibration techniques. In general, the embodiments described herein calibrate by measuring output values from an ADC with a known calibration input values being applied. The measured output values are used to determine localized polynomial interpolants. Each of the determined localized polynomial interpolants is then evaluated at an uncorrected output value, and the evaluated localized polynomial interpolants are then used to generate correction values. These correction values can then be used to calibrate the ADC during later operation. Such a calibration technique can provide effective calibration for a variety of ADCs, including ADCs that use inverter-based voltage-to-current (VI) converters and current-controlled ring oscillators.
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公开(公告)号：EP2489129B1
公开(公告)日：2015-02-25
申请号：EP11714316.4
申请日：2011-04-14
发明人： VÖLKER, Matthias , BERGS, Joakim , HAUER, Johann
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公开(公告)号：EP2414782B1
公开(公告)日：2014-11-12
申请号：EP09779253.5
申请日：2009-04-03
发明人： HASLER, David , MASA, Peter , HEIM, Pascal , FRANZI, Edoardo
CPC分类号： G01D5/34746 , G01D5/24438 , G01D5/24452 , G01D5/24476 , G01D5/2449 , G01D5/2495 , G01D5/34792 , H03M1/0678 , H03M1/202 , H03M1/282
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公开(公告)号：EP2489129A1
公开(公告)日：2012-08-22
申请号：EP11714316.4
申请日：2011-04-14
发明人： VÖLKER, Matthias , BERGS, Joakim , HAUER, Johann
摘要： An apparatus for determining a measurement value for the oscillations of an oscillator having a plurality of phase outputs that have occurred in one reference interval includes at least one counter connected to a predetermined phase output of the oscillator and incremented at a predetermined change of state of the phase output. Further, the apparatus comprises an evaluation means connected to the plurality of phase outputs and the counter, wherein the evaluation means is implemented to determine, at the end of the reference interval, a relative phase value of the oscillator with respect to the phase value associated with the predetermined phase output, and to determine the measurement value by using the count at the end of the reference interval and by using the relative phase value.
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公开(公告)号：EP2423645A2
公开(公告)日：2012-02-29
申请号：EP11187183.6
申请日：2009-04-03
发明人： Hasler, David , Masa, Peter , Heim, Pascal , Franzi, Edoardo
CPC分类号： G01D5/34746 , G01D5/24438 , G01D5/24452 , G01D5/24476 , G01D5/2449 , G01D5/2495 , G01D5/34792 , H03M1/0678 , H03M1/202 , H03M1/282
摘要： The present invention discloses a one-dimension position measurement system comprising:
- a first ruler, on which is applied a first one-dimension code,
- a second ruler, on which is applied a second one-dimension code,
- a camera for acquiring simultaneously a picture of a portion of the first one-dimension code and of a portion of the second one-dimension code, and
- some processing means.
According to the invention, the second ruler is disposed parallel to the first ruler, one end of said first ruler being tied to one end of said second ruler, the other end of said first and second rulers being free. Moreover, said first and second rulers are made of material having different temperature expansion coefficients.摘要翻译： 本发明公开了一种一维位置测量系统，包括： - 第一尺，在第一尺上施加第一一维码， - 第二尺，在第二尺上施加第二一维码， - 摄像机，用于采集 同时显示第一一维代码的一部分和第二一维代码的一部分的图片以及一些处理装置。 根据本发明，第二直尺平行于第一直尺设置，所述第一直尺的一端系在所述第二直尺的一端，所述第一直尺和第二直尺的另一端是自由的。 而且，所述第一尺和第二尺由具有不同温度膨胀系数的材料制成。
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公开(公告)号：EP2162989A2
公开(公告)日：2010-03-17
申请号：EP08776504.6
申请日：2008-06-25
申请人： NXP B.V.
发明人： BRIAIRE, Joseph
CPC分类号： H03M1/0678 , H03M1/0682 , H03M1/742
摘要： A current-steered DAC has first and second differential outputs for providing an analog output signal under control of a digital input signal. In operational use of the DAC, the output signal has a differential component, which is representative of the digital input signal, and also has a first common-mode component. The DAC has circuitry operative to add an extra common-mode component to both the first and second differential outputs so as to make a sum of the first common-mode component and the extra common-mode component substantially independent of a state change of the digital input signal.
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公开(公告)号：EP0914717B1
公开(公告)日：2003-08-06
申请号：EP98915053.7
申请日：1998-05-07
IPC分类号： H03M1/66
CPC分类号： H03M1/0678 , H03M1/742
摘要： A digital to analogue converter comprises a plurality of current sources (T0-Tn) and corresponding selection switches (D0-Dn) which connect the current sources to an output (3). In order to enable a constant capacitance to be presented at the output (3) regardless of the input digital code a plurality of dummy current sources ( T 0- T n) which take the same form as the current sources (T0-Tn) are provided. The dummy current sources have associated selection switches ( D 0- D n) which are operated by the logical inverse of the code applied to the current sources (T0-Tn).
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公开(公告)号：EP1222741A2
公开(公告)日：2002-07-17
申请号：EP00964860.1
申请日：2000-09-15
发明人： WIKNER, Jacob , VESTERBACKA, Mark
IPC分类号： H03M1/66
CPC分类号： H03M1/0678 , H03M1/0663 , H03M1/0673 , H03M1/745
摘要： A D/A converter includes a triangular unit weight array (WA). A decoder (D) transforms digital samples into control signals (x[1], ..., x[5]) having a linearly weighted binary representation. These control signals are used for activation/deactivation of entire rows (columns) of the triangular unit weight array. Finally the unit weights are combined into an analog output signal.
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9.发明公开Noise cancellation in mixed signal environment 失效Rauschunterdrückung在einer Umgebung mit gemischten Signalen
公开(公告)号：EP0874326A2
公开(公告)日：1998-10-28
申请号：EP98302851.5
申请日：1998-04-14
发明人： Liu, Edward W.
CPC分类号： H03M1/0678 , G06J1/00 , H03M3/35 , H03M3/458 , H03M3/50
摘要： A method of canceling noise in analog circuits is described along with noise cancellation circuits. Analog circuits are sensitive to noise. Especially in mixed signal environments where digital circuits and analog circuits are combined, the noise generated by relatively noisy digital circuits often cause the analog circuits to produce incorrect output signals. Instead of shielding or separating the susceptible analog circuits from noisy digital circuits, additional circuitry is added where one of the added circuits, denoted as the noise separator circuit, produce only the noise component of the output signal, the first output, of the analog circuit adversely affected by the noise. Then, another circuit is used to subtract the noise from the first output, thereby producing a noise-free output signal. Alternatively, the noise separator circuit can be made to produce the inverse of the first output, including the inverse of the noise. Then, the first output and the inverse output can be added and halved to produce the desired, noise-free output.
摘要翻译： 在模拟电路中消除噪声的方法与噪声消除电路一起被描述。 模拟电路对噪声敏感。 特别是在组合数字电路和模拟电路的混合信号环境中，由相对嘈杂的数字电路产生的噪声通常会导致模拟电路产生不正确的输出信号。 代替将敏感模拟电路屏蔽或分离噪声数字电路，添加附加电路，其中附加电路之一（表示为噪声分离器电路）仅产生模拟电路的输出信号的第一输出的噪声分量 受到噪音的不利影响。 然后，使用另一个电路从第一输出中减去噪声，从而产生无噪声的输出信号。 或者，可以使噪声分离器电路产生第一输出的倒数，包括噪声的倒数。 然后，可以将第一输出和反相输出相加并减半以产生所需的无噪声输出。
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10.发明公开
公开(公告)号：EP0393728A2
公开(公告)日：1990-10-24
申请号：EP90110749.0
申请日：1986-09-09
IPC分类号： H03M1/66
CPC分类号： H03M1/0872 , H03K5/023 , H03K17/6871 , H03K17/693 , H03K19/018564 , H03M1/0678 , H03M1/745
摘要： An n-bit current switching digital-to-analog converter of the type in which each weighted current I k , k=1, ..., n, of a set of n weighted currents has an associated current steering switch, said digital-to-analog converter comprises:
a plurality of input means (201,203,205,209), each input means coupled to an associated current steering switch (211), each input means (201,203,205,209) inputting a data signal representative of one bit of an n-bit data word, at a predetermined data rate, to said associated current steering switch, said current steering switch (211) responsive to said data signal to conduct I k to a first summing rail (RAIL) when the data signal is of a first value and to conduct I k to a second summing rail (RAILBAR) when the data signal is of a second value;
current source means (1) coupled to said current steering switches (211) for providing said set of n weighted currents; and
sampling means (9) coupled to the first and second summing rails (RAIL, RAILBAR) for providing a first and second output (321,317), respectively, said first and second output (321,317) representing a sample of the summed currents on the first and second summing rails (RAIL, RAILBAR) after the current has settled to a steady-state value and prior to a succeeding data transition.摘要翻译： 一种n位电流切换数模转换器，其中一组n个加权电流的每个加权电流I k，k = 1，...，n具有相关联的电流转向开关，所述数字到 - 数值转换器包括：多个输入装置（201,203,205,209），每个输入装置耦合到相关联的电流转向开关（211），每个输入装置（201,203,205,209）输入表示n位数据字的一位的数据信号， 以预定的数据速率传送到所述相关联的电流转向开关，当数据信号为第一值时，所述当前转向开关（211）响应于所述数据信号将Ik导通到第一求和轨（RAIL），并且使Ik 当数据信号为第二值时，第二加法轨（RAILBAR）; 耦合到所述电流转向开关（211）的电流源装置（1），用于提供所述一组n个加权电流; 以及耦合到所述第一和第二求和轨道（RAIL，RAILBAR）的采样装置（9），用于分别提供第一和第二输出（321,317），所述第一和第二输出（321,317）表示第一和第二输出 和电流已经稳定在稳态值之后，以及在成功的数据转换之前的第二个相加轨（RAIL，RAILBAR）。
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