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公开(公告)号：EP0146938B1
公开(公告)日：1991-02-20
申请号：EP84115977.5
申请日：1984-12-20
申请人： ALCATEL N.V.
CPC分类号： H03K5/1252 , G01R19/16557 , G01R29/0273 , H04Q1/32
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112.发明公开
公开(公告)号：EP0396562A1
公开(公告)日：1990-11-14
申请号：EP88909762.0
申请日：1988-11-10
CPC分类号： H04L12/5602 , H04J3/247 , H04L2012/5636 , H04L2012/5684
摘要： On utilise l'équipement de mesure (SMC) dans un système de commutation de télécommunications, afin de contrôler si la vitesse des cellules de chacune d'une pluralité de chaînes de cellules individuelles multiplexées dans une même liaison, reste dans les limites sur la base desquelles son multiplexage a été permis. A cet effet, ledit équipement contrôle à la fin de chaque intervalle de mesure (MTI), et pour une pluralité de vitesses de cellules [(MS)/A, (MS/2)/A,...], si les probabilités susceptibles de dépasser ces vitesses de cellules sont dépassées ou non. Si c'est le cas, la vitesse des cellules est limitée par des cellules de dérivation. Ainsi une fonction de répartition de probabilité cumulative complémentaire attendue (par rapport à 1) de la vitesse des cellules est approchée par une fonction en forme de cage d'escalier.
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公开(公告)号：EP0340870A3
公开(公告)日：1990-06-13
申请号：EP89201120.6
申请日：1989-05-01
CPC分类号： H03C3/0975 , H03C3/0925 , H03C3/0933 , H03C3/0941 , H03L7/1978
摘要： The digital modulator shown in Fig. 2 provides at its output SO a signal whose frequency f1 is equal to the product of a clock frequency f2, applied to its input CLI, a second integer P by which a divider DIV2 divides, and a factor equal to the sum of another integer N′ by which a divider DIV3 divides, and a rational number (F′+M)/P. Because the latter is smaller than unity use can be made of a well known accumulator ACC and of a single-cycle removing circuit CRC. With f2=3.25 MHz, P=16, N′=17, the following modulated carrier frequencies may for instance be obtained : wherein M = with m varying between 0 and 519 and
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公开(公告)号：EP0283079A3
公开(公告)日：1990-05-30
申请号：EP88200411.2
申请日：1988-03-05
IPC分类号： H04J3/06
CPC分类号： H04J3/0632 , H04J3/0658 , H04L12/1813
摘要： Asynchronous time division system including at least one node with a switching network (BSN) to which a plurality of user stations (US1/N) are coupled via transmission links and which is adapted to interconnect user stations. At least one (US4) of these user stations is a clock station providing clock information, and upon the establishment of a connection between a plurality of other user stations (US1/3), with the purpose of exchanging synchronous data, each of these stations establishes a connection with this clock station.
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公开(公告)号：EP0357618A1
公开(公告)日：1990-03-14
申请号：EP88902469.0
申请日：1988-03-11
IPC分类号： H04L12
CPC分类号： H04L49/103 , H04L49/505 , H04L49/557
摘要： Système de commutation (SW) pour le transfert de paquets de signaux numériques comportant une partie en-tête contenant des information d'acheminement provenant d'une pluralité de terminaux d'entrée (R1 à R16) vers une pluralité de terminaux de sortie (T1 à T16), la destination du terminal de sortie pour un paquet donné étant choisi selon les informations d'acheminement dudit paquet. Le système comporte une pluralité de mémoires (M1 à M8) dont chacune est divisée en une pluralité de zones de stockage, chacune étant associée à un terminal de sortie respectif, des circuits de répétion (RC1 à RC16) servant à diviser chaque paquet reçu en une pluralité de sous-paquets, des circuits de commande (CC1 à CC8) et des circuits de transmission (TC1 à TC16) afin de reconstituer un paquet à partir de ces sous-paquets. Selon les instructions des circuits de commande qui fonctionnent selon les informations d'acheminement d'un paquet, les sous-paquets faisant partie de ce paquet sont transmis aux mémoires respectives et chargés dans les zones de stockage de celle-ci en fonction du terminal de sortie de destination.
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公开(公告)号：EP0257687A3
公开(公告)日：1989-12-20
申请号：EP87201504.5
申请日：1987-08-06
申请人： ALCATEL N.V.
摘要： A digital transmission system including a digital signal generator (GEN) able to generate a rectangular output signal (SX2, SX2ʹ) , e.g. in the audible frequency range. The frequency and the amplitude of this output signal are respectively determined by the frequency (500/16,000 Hz) of a square wave (SQ1, SQ1ʹ) and by the duty cycle of a rectangular wave (SE0) both waves being created in the generator under control of an incoming digital word, the rectangular wave chopping the square wave. The frequency content of the spectrum of the output signal is identical to that of the square wave.
摘要翻译： 包括能够产生矩形输出信号（SX2，SX2'）的数字信号发生器（GEN）的数字传输系统， 在可听频率范围内。 该输出信号的频率和幅度分别由方波（SQ1，SQ1'）的频率（500 / 16,000Hz）和在发电机中产生的矩形波（SE0）两个波的占空比确定 控制输入的数字字，矩形波斩波方波。 输出信号频谱的频率成分与方波的频谱成分相同。
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117.发明公开
公开(公告)号：EP0340870A2
公开(公告)日：1989-11-08
申请号：EP89201120.6
申请日：1989-05-01
CPC分类号： H03C3/0975 , H03C3/0925 , H03C3/0933 , H03C3/0941 , H03L7/1978
摘要： The digital modulator shown in Fig. 2 provides at its output SO a signal whose frequency f1 is equal to the product of a clock frequency f2, applied to its input CLI, a second integer P by which a divider DIV2 divides, and a factor equal to the sum of another integer N′ by which a divider DIV3 divides, and a rational number (F′+M)/P. Because the latter is smaller than unity use can be made of a well known accumulator ACC and of a single-cycle removing circuit CRC. With f2=3.25 MHz, P=16, N′=17, the following modulated carrier frequencies may for instance be obtained : wherein M = with m varying between 0 and 519 and
摘要翻译： 图1所示的数字调制器。 2在其输出端SO提供一个信号，其频率f1等于应用于其输入CLI的时钟频率f2的乘积，除法器DIV2除以的第二整数P和等于另一整数N之和的因子 分频器DIV3分频，有理数（F min + M）/ P。 由于后者小于单位，所以可以使用众所周知的累加器ACC和单周期去除电路CRC。 对于f2 = 3.25MHz，P = 16，N min = 17，可以获得以下调制的载波频率：其中M = @@@，其中m在0和519之间变化，并且
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公开(公告)号：EP0322026A3
公开(公告)日：1989-09-27
申请号：EP88202852.5
申请日：1988-12-13
IPC分类号： H04J3/16
CPC分类号： H04J3/247
摘要： Conditional multiplexer wherein an input bitstream having a variable bitrate is allowed as part of a multiplexed output bitstream of input bitstreams or not depending on the result of an operation performed by processing means (TPR1) and which consists in calculating an estimated output bandwidth (B2) of said output bitstream from the mean values (mi) and variances (vi) of the probability distribution functions of the bitrates of said input bitstreams and in the subsequent comparison of said estimated output bandwidth (B2) with the maximum allowable output bandwidth (B). Further processing means (RPR1) continuously measure the mean and variance parameters and continuously verify if the sources of the bitstreams operate within the assigned bandwidths.
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公开(公告)号：EP0216765B1
公开(公告)日：1989-09-13
申请号：EP85902026.5
申请日：1985-04-18
申请人： ALCATEL N.V.
CPC分类号： H04B10/6911 , H03F3/082 , H04B10/69
摘要： Optical receiver with a bias circuit (T8, R2/3, R44/45) adapted to reversely bias a photodiode (PIN). This bias circuit for increasing optical power levels shifts the operating point of the photodiode (PIN) towards and into the nonlinear operating region of the photodiode which then becomes forwardly biased and for optical power levels above a predetermined value operates as a constant current source supplying a constant current (Ic) to said photodiode (PIN).
摘要翻译： 带偏置电路（T8，R2 / 3，R44 / 45）的光接收器适用于反向偏置光电二极管（PIN）。 用于增加光功率电平的偏置电路将光电二极管（PIN）的工作点移向光电二极管的非线性工作区域，并且光电二极管的非线性工作区域然后变为正向偏置，并且对于高于预定值的光功率级别作为恒定电流源工作， 恒定电流（Ic）到所述光电二极管（PIN）。
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公开(公告)号：EP0322026A2
公开(公告)日：1989-06-28
申请号：EP88202852.5
申请日：1988-12-13
IPC分类号： H04J3/16
CPC分类号： H04J3/247
摘要： Conditional multiplexer wherein an input bitstream having a variable bitrate is allowed as part of a multiplexed output bitstream of input bitstreams or not depending on the result of an operation performed by processing means (TPR1) and which consists in calculating an estimated output bandwidth (B2) of said output bitstream from the mean values (mi) and variances (vi) of the probability distribution functions of the bitrates of said input bitstreams and in the subsequent comparison of said estimated output bandwidth (B2) with the maximum allowable output bandwidth (B). Further processing means (RPR1) continuously measure the mean and variance parameters and continuously verify if the sources of the bitstreams operate within the assigned bandwidths.
摘要翻译： 条件多路复用器，其中根据由处理装置（TPR1）执行的操作的结果，允许具有可变比特率的输入比特流作为输入比特流的多路复用输出比特流的一部分，并且包括计算估计的输出带宽（B2） 根据所述输入比特流的比特率的概率分布函数的平均值（mi）和方差（vi）以及随后的所述估计输出带宽（B2）与最大允许输出带宽（B）的比较， 。 进一步的处理装置（RPR1）连续地测量平均值和方差参数，并连续验证比特流的源是否在分配的带宽内运行。
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