利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

754 条记录 (耗时 0.017 秒)

    SAMPLE AND HOLD APPARATUS
    181.
    发明授权
    SAMPLE AND HOLD APPARATUS 有权
    探头和保持装置

    公开(公告)号：EP1842204B1

    公开(公告)日：2010-12-29

    申请号：EP06718939.9

    申请日：2006-01-20

    申请人： Analog Devices, Inc.

    发明人： BREWER, Robert J. ,  LYDEN, Colin G. ,  COLN, Michael C.W.

    IPC分类号： G11C27/02

    CPC分类号： G11C27/026 ,  G11C27/024

    摘要： An acquisition and averaging circuit is provided in which, during a sampling phase capacitors in sample blocks 4 and 6 are sequentially connected to the input signal to sample it and are then isolated so as to hold the sample. The capacitors are then connected to a combining/averaging arrangement such that an average of the sample values is formed.

    ACTIVE CURRENT MODE SAMPLING CIRCUIT
    185.
    发明授权
    ACTIVE CURRENT MODE SAMPLING CIRCUIT 有权
    活动功率模式取样

    公开(公告)号：EP1668647B1

    公开(公告)日：2009-09-16

    申请号：EP03818777.9

    申请日：2003-09-29

    申请人： Nokia Corporation

    发明人： RUHA, Antti ,  TERVALUOTO, Jussi-Pekka ,  RUOTSALAINEN, Tarmo

    IPC分类号： G11C27/02 ,  H03H19/00

    CPC分类号： G11C27/026 ,  G11C27/028 ,  H03G1/0094 ,  H03H19/004

    摘要： The invention relates to an active current mode sampling circuit comprising an operational amplifier (103) and at least one switched capacitor (C2, C2a, C2b). In order to reduce the power consumption of such a circuit, first switching elements (S101a, S101b, S102a, S102b) switch the switched capacitor (C2, C2a, C2b) between an input and an output of the operational amplifier (103) during charging phases phi1. Further, second switching elements (S103a, S103b, S104a, S104b) connect the switched capacitor (C2, C2a, C2b) during discharging phases phi2 to a subsequent stage (104), in order to provide a charge of the switched capacitor (C2, C2a, C2b) to the subsequent stage (104). The invention relates equally to a device (107) comprising such a sampling circuit and to a method of operating such a sampling circuit.

    Methods and apparatus for measuring current as In sensing a memory cell
    186.
    发明公开
    Methods and apparatus for measuring current as In sensing a memory cell 有权
    用于测量作为存储单元的电流的方法和装置，

    公开(公告)号：EP2045817A1

    公开(公告)日：2009-04-08

    申请号：EP08167579.5

    申请日：2004-06-09

    申请人： Micron Technology, Inc.

    发明人： Baker, R Jacob

    IPC分类号： G11C29/00 ,  G11C27/02 ,  G11C11/15

    CPC分类号： G11C27/024 ,  G11C7/06 ,  G11C11/1659 ,  G11C11/1673 ,  G11C2207/061

    摘要： Apparatus and methods sense or measure an input current (I in ), such as a current indicating a logic state of a memory cell (38). A sensing circuit includes an amplifier (412), a capacitor (422), a current source circuit (430), a clocked comparator (426) and a clocked counter (448). The current source circuit operates responsive to an output (444,445) of the comparator to supply or withdraw current to and from the capacitor during respective charging and discharging intervals. The count in the clocked counter results from periodic comparisons of the capacitor voltage with a reference voltage and is, therefore, related to the logic state of the memory cell. The magnitude of current supplied during charging is less than the magnitude withdrawn during discharging, allowing use of a smaller counter.

    摘要翻译： 装置和方法感测或输入电流的量度（I在）：诸如当前指示的存储单元（38）的逻辑状态。 感测电路包括放大器（412），电容器（422），一个电流源电路（430），一个时钟控制比较器（426）和一个时钟计数器（448）。 响应于所述电流源电路的充电和放电respectivement间隔期间对比较器供应或撤回的电流和从所述电容器的输出（444.445）进行操作。 在计数器的计数值时钟与参考电压从电容器电压的周期性的比较结果，并且，因此，与所述存储器单元的逻辑状态。 在充电期间提供的电流的量值是小于放电，从而允许使用较小的计数器的过程中取出的幅度。

    APPARATUS FOR MEASURING CURRENT IN SENSING A MEMORY CELL
    187.
    发明授权
    APPARATUS FOR MEASURING CURRENT IN SENSING A MEMORY CELL 有权
    设备用于测量电流读取存储单元

    公开(公告)号：EP1634301B1

    公开(公告)日：2008-12-31

    申请号：EP04754483.8

    申请日：2004-06-09

    申请人： Micron Technology, Inc.

    发明人： BAKER, R., Jacob

    IPC分类号： G11C29/00 ,  G11C27/02 ,  G11C11/15

    CPC分类号： G11C27/024 ,  G11C7/06 ,  G11C11/1659 ,  G11C11/1673 ,  G11C2207/061

    摘要： Apparatus and methods sense or measure an input current, such as a current indicating a logic state of a memory cell. A sensing circuit includes an amplifier, a capacitor, a current source circuit, a clocked comparator and a clock counter. The current source circuit operates responsive to an output of the comparator to supply or withdraw current to and from the capacitor during respective charging and discharging intervals. The count in the clocked counter results from periodic comparisons of the capacitor voltage with a reference voltage and is, therefore, related to the logic state of the memory cell. The magnitude of current supplied during charging is less than the magnitude withdrawn during discharging, allowing use of a smaller counter.

    DOUBLE INPUT BUFFER FOR TRACK-AND-HOLD AMPLIFIER
    188.
    发明授权
    DOUBLE INPUT BUFFER FOR TRACK-AND-HOLD AMPLIFIER 有权
    双输入缓存样本和STOP EVER STRONG

    公开(公告)号：EP1157389B1

    公开(公告)日：2008-10-22

    申请号：EP00990727.0

    申请日：2000-12-13

    申请人： NXP B.V.

    发明人： HOOGZAAD, Gian

    IPC分类号： G11C27/02

    CPC分类号： G11C27/026

    摘要： The present invention relates to an input buffer for a switched emitterfollower-like track-and-hold amplifier comprising an input stage with an input transistor (Q1), a first diode (Q2, Q2b), a cathode side of which first diode (Q2, Q2b) is connected to an emitter of the input transistor (Q1), a first current source (4) between on the one hand the junction between the cathode of the first diode (Q2, Q2b) and the emitter of the input transistor (Q1) and on the other hand a first supply voltage line (2), an anode of the first diode (Q2, Q2b) being connected to a track-and-hold controlled emitterfollower (6). The first current source (4) is a non-switched constant current source, and a second current source (M1) is connected between a collector of the input transistor (Q1) and a second supply voltage (3). A second transistor (M2, M2b) comprising a control electrode, a current input electrode and a current output electrode is connected with the control electrode to the junction (n1) between the collector of the input transistor (Q1) and the second current source (M1), with the current input electrode to the second supply voltage (3) and with the current output electrode to the anode of the first diode (Q2, Q2b).

    SAMPLED-DATA CIRCUITS USING ZERO CROSSING DETECTION
    190.
    发明公开
    SAMPLED-DATA CIRCUITS USING ZERO CROSSING DETECTION 有权
    使用零交叉检测的采样数据电路

    公开(公告)号：EP1899979A1

    公开(公告)日：2008-03-19

    申请号：EP06774451.6

    申请日：2006-06-30

    申请人： Cambridge Analog Technology, LLC

    发明人： LEE, Hae-Seung

    IPC分类号： G11C27/02

    CPC分类号： G11C27/024 ,  H03H19/004 ,  Y10T307/74

    摘要： A sampled-data analog circuit includes a level-crossing detector (30). The level-crossing detector controls sampling switches (s22n, s23n, s22p, s23p) to provide a precise sample of the output voltage when the level-crossing detector senses the predetermined level crossing of the input signal. The level-crossing detection may be a zero-crossing detection. An optional common-mode feedback circuit (400) can keep the output common-mode voltage substantially constant.

    摘要翻译： 采样数据模拟电路包括电平交叉检测器（30）。 当电平交叉检测器检测到输入信号的预定电平交叉时，电平交叉检测器控制采样开关（s22n，s23n，s22p，s23p）以提供输出电压的精确采样。 电平交叉检测可以是零交叉检测。 可选的共模反馈电路（400）可以保持输出共模电压基本恒定。