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公开(公告)号：EP1726089A1
公开(公告)日：2006-11-29
申请号：EP04704299.9
申请日：2004-01-22
申请人： Nokia Corporation
IPC分类号： H03D7/14
CPC分类号： H03D7/14
摘要： The invention relates to a mixer circuit 31 comprising a down-conversion mixing component 33 arranged for down-converting an input radio frequency signal Irf+, Irf-. In order to improve such a mixer circuit, it is proposed that it comprises in addition an active mixer load circuit 34 connected to output terminals of the mixing component. The active mixer load circuit includes an active mixer load 51, T1, T2 and modulating means S1-S4 arranged for modulating a flicker noise produced by the active mixer load away from the signal band of a signal Ibb+, Ibb- output by the down-conversion mixing component. The invention relates equally to a receiver, a chip and a device comprising such a mixer circuit and to a method for use with such a mixer circuit.
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2.发明授权A MULTI-LEVEL QUANTIZER WITH CURRENT MODE DEM SWITCH MATRICES AND SEPARATE DEM DECISION LOGIC FOR A MULTIBIT SIGMA DELTA MODULATOR 有权WITH MEHRPEGELQUANTISIERER功耗模式-THE-开关矩阵和独立的决策逻辑用于多Σ-Δ调制
公开(公告)号：EP1400017B1
公开(公告)日：2011-04-27
申请号：EP02735826.6
申请日：2002-06-12
申请人： Nokia Corporation
摘要： A multilevel quantizer (14) is provided in combination with dynamic element matching DEM (20) circuitry in a multibit sigma-delta modulator (10). The DEM circuitry is implemented in a divided manner as two major component parts: at least one current mode DEM switch matrix (20B)(SM), and an associated DEM decision logic block that implements the DEM control algorithm (20A) and that controls the SM. The DEM decision logic block is removed from the delay sensitive sigma-delta feedback loop, while the DEM SM remains within the feedback loop. Also described is a convenient and efficient technique to implement the DEM SM, using current steering logic within the multibit quantizer. In this case one or more DEM switching matrices may be provided within the quantizer for reordering the N-1 digital output bits of the N-level quantizer.
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公开(公告)号：EP1726089B1
公开(公告)日：2010-09-22
申请号：EP04704299.9
申请日：2004-01-22
申请人： Nokia Corporation
IPC分类号： H03D7/14
CPC分类号： H03D7/14
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公开(公告)号：EP1668647B1
公开(公告)日：2009-09-16
申请号：EP03818777.9
申请日：2003-09-29
申请人： Nokia Corporation
CPC分类号： G11C27/026 , G11C27/028 , H03G1/0094 , H03H19/004
摘要： The invention relates to an active current mode sampling circuit comprising an operational amplifier (103) and at least one switched capacitor (C2, C2a, C2b). In order to reduce the power consumption of such a circuit, first switching elements (S101a, S101b, S102a, S102b) switch the switched capacitor (C2, C2a, C2b) between an input and an output of the operational amplifier (103) during charging phases phi1. Further, second switching elements (S103a, S103b, S104a, S104b) connect the switched capacitor (C2, C2a, C2b) during discharging phases phi2 to a subsequent stage (104), in order to provide a charge of the switched capacitor (C2, C2a, C2b) to the subsequent stage (104). The invention relates equally to a device (107) comprising such a sampling circuit and to a method of operating such a sampling circuit.
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公开(公告)号：EP1668647A1
公开(公告)日：2006-06-14
申请号：EP03818777.9
申请日：2003-09-29
申请人： Nokia Corporation
CPC分类号： G11C27/026 , G11C27/028 , H03G1/0094 , H03H19/004
摘要： The invention relates to an active current mode sampling circuit comprising an operational amplifier (103) and at least one switched capacitor (C2, C2a, C2b). In order to reduce the power consumption of such a circuit, first switching elements (S101a, S101b, S102a, S102b) switch the switched capacitor (C2, C2a, C2b) between an input and an output of the operational amplifier (103) during charging phases φ1. Further, second switching elements (S103a, S103b, S104a, S104b) connect the switched capacitor (C2, C2a, C2b) during discharging phases φ2 to a subsequent stage (104), in order to provide a charge of the switched capacitor (C2, C2a, C2b) to the subsequent stage (104). The invention relates equally to a device (107) comprising such a sampling circuit and to a method of operating such a sampling circuit.
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6.发明公开METHOD AND APPARATUS FOR SUPPRESSING TONES INDUCED BY CYCLIC DYNAMIC ELEMENT MATCHING (DEM) ALGORITHMS 有权用于抑制由循环动态元素匹配（DEM）算法引起的音调的方法和设备
公开(公告)号：EP1402644A2
公开(公告)日：2004-03-31
申请号：EP02735842.3
申请日：2002-06-13
申请人： Nokia Corporation
摘要： Disclosed is a method and apparatus for performing Dynamic Element Matching (DEMs 12/14). The method operates to input a plurality of digital values and, for each value, to generate a plurality of N signals intended respectively to drive a plurality of N elements. The plurality of signals are generated (12) so as to average the usage of individual elements over time. The method further rearranges (14) the signals so as to suppress the generation of undesired tones. Periodic rearrangement occurs only at a time when an enable signal that is input to a secondary DEM (14) from a primary DEM (12). Signals are generated by the primary DEM (12) using a cyclic DEM algorithm, and the periodic rearrangment performed by the secondary DEM (14) is preferably based on randomization or pseudo-randomization.
摘要翻译： 公开了用于执行动态元素匹配（DEM 12/14）的方法和装置。 该方法操作以输入多个数字值，并且对于每个值来产生分别旨在驱动多个N个元件的多个N个信号。 生成多个信号（12）以便随时间平均化各个元素的使用。 该方法进一步重新排列（14）信号以抑制不需要的音调的产生。 仅当从主DEM（12）输入到辅DEM（14）的启用信号时才发生周期性重排。 信号由主DEM（12）使用循环DEM算法生成，并且由次DEM（14）执行的周期性重排优选地基于随机化或伪随机化。
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公开(公告)号：EP1433259A2
公开(公告)日：2004-06-30
申请号：EP02762725.6
申请日：2002-09-20
申请人： Nokia Corporation
IPC分类号： H03M3/00
摘要： A multimode communications device includes an RF section and an analog-to-digital converter (ADC) located in a receive path between the RF section and a baseband section. The ADC includes a programmable signal converter core operable to perform ADC functions on a received RF signal in accordance with different types of mobile communication device operational modes, and further includes a multimode control function for programming the signal converter core as a function of a currently selected operational mode. The programmable signal converter core preferably includes a sigma-delta modulator, and a signal analysis function is provided for analyzing the received RF signal for dynamically programming the converter core to adapt to temporary signal and interference conditions by increasing or decreasing the performance of the signal converter. The signal analysis function may be embodied as a decimation filter having an input coupled to an output of the modulator, or by a digital signal processor forming a portion of a baseband section. The programmable signal converter core may be programmed to change the number of bits used by the sigma-delta modulator and/or a loop filter transfer function and loop filter coefficients, or a number of quantizer levels, or decimator coefficients and word width. The sigma-delta modulator bias currents may also be changed, as may a selected type of dynamic element matching function, each as a function of the selected mode. Other operational criteria that can be changed include the sigma-delta modulator oversampling ratio and/or a change from a switched capacitor to a resistor-capacitor circuit technique, or vice versa.
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8.发明公开A MULTI-LEVEL QUANTIZER WITH CURRENT MODE DEM SWITCH MATRICES AND SEPARATE DEM DECISION LOGIC FOR A MULTIBIT SIGMA DELTA MODULATOR 有权WITH MEHRPEGELQUANTISIERER功耗模式-THE-开关矩阵和独立的决策逻辑用于多Σ-Δ调制
公开(公告)号：EP1400017A2
公开(公告)日：2004-03-24
申请号：EP02735826.6
申请日：2002-06-12
申请人： Nokia Corporation
IPC分类号： H03K3/00
摘要： A multilevel quantizer (14) is provided in combination with dynamic element matching DEM (20) circuitry in a multibit sigma-delta modulator (10). The DEM circuitry is implemented in a divided manner as two major component parts: at least one current mode DEM switch matrix (20B)(SM), and an associated DEM decision logic block that implements the DEM control algorithm (20A) and that controls the SM. The DEM decision logic block is removed from the delay sensitive sigma-delta feedback loop, while the DEM SM remains within the feedback loop. Also described is a convenient and efficient technique to implement the DEM SM, using current steering logic within the multibit quantizer. In this case one or more DEM switching matrices may be provided within the quantizer for reordering the N-1 digital output bits of the N-level quantizer.
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9.发明授权MULTIMODE I/O CIRCUITRY SUPPORTING LOW INTERFERENCE SIGNALING SCHEMES FOR HIGH SPEED DIGITAL INTERFACES 有权更符合-I / O电路，问题较差的信号格式新快速数字接口支持
公开(公告)号：EP1446883B1
公开(公告)日：2012-04-04
申请号：EP02802339.8
申请日：2002-10-17
申请人： Nokia Corporation
IPC分类号： H03K19/094 , H03K19/173 , H03K19/177 , H04L25/02 , H03K19/0185
CPC分类号： H04L25/0272 , H01L2224/48091 , H01L2224/49175 , H01L2924/13091 , H01L2924/30107 , H01L2924/3011 , H04L25/0264 , H04L25/0282 , H04L25/0294 , H04L25/45 , H01L2924/00014 , H01L2924/00
摘要： A multi-mode I/0 circuit or cell (10) is provided for transmitting and receiving data between ICs, where each IC contains at least one of the I/0 circuits. Each data link includes transmitter circuitry (12) and receiver circuitry (14). The transmitter circuitry sends data to a receiver circuitry in another IC, and the receiver circuitry receives data from a transmitter circuitry in another IC.
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10.发明授权METHOD AND APPARATUS FOR SUPPRESSING TONES INDUCED BY CYCLIC DYNAMIC ELEMENT MATCHING (DEM) ALGORITHMS 有权方法和设备的声音所造成的算法（循环动态元件匹配）抑制
公开(公告)号：EP1402644B1
公开(公告)日：2007-08-01
申请号：EP02735842.3
申请日：2002-06-13
申请人： Nokia Corporation
摘要： Disclosed is a method and apparatus for performing Dynamic Element Matching (DEM). The method operates to input a plurality of digital values and, for each value, to generate a plurality of N signals individual ones of which are intended to drive one of a plurality of N elements. The plurality of signals are generated so as to average the usage of individual ones of the N elements over time. The method further periodically rearranges the plurality of N signals so as to suppress the generation of undesired periodicities or tones in the usage of the N elements, and without affecting the averaging of the usage of the N elements. Preferably the periodic rearrangement occurs only at a time when the usage of the N elements is indicated as being averaged using, for example, an enable signal that is input to a secondary DEM block from a primary DEM block. The plurality of N signals are preferably generatd by the primary DEM block using a cyclic DEM algorithm, such as a Data Weighted Averaging (DWA) algorithm or a rotation-based Clocked Averaging (CLA) algorithm, and the periodic rearrangment performed by the secondary DEM block is preferably based on randomization or pseudo-randomization.
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