-
公开(公告)号：EP1286358A1
公开(公告)日：2003-02-26
申请号：EP01305427.5
申请日：2001-06-22
IPC分类号： G11C29/00
摘要： Apparatus for testing an integrated circuit, the integrated circuit comprising a plurality of semiconductor memory cells connected by a common word-line, each memory cell comprising: respective first and second transistors in cross-coupled arrangement to form a bistable latch, the drain of the first transistor representing a respective first node for storing a high or low potential state and being connected to a respective first semiconductor arrangement for replacing charge leaked from the first node and being connected to a respective first switching means, activatable by the common word-line, for coupling the respective first node to a respective first bit-line, the drain of the second transistor representing a respective second node for storing a high or low potential state and being connected to a respective second semiconductor arrangement for replacing charge leaked from the respective second node and being connected to a respective second switching means, activatable by the common word line, for coupling the second node to a respective second bit-line; and a respective individual gate arrangement having an output, and inputs connected to the respective first and second bit-lines, and being arranged to provide an output of a first type when the respective first and second bit lines are both within a low potential range, and otherwise provide an output of a second type; and the apparatus comprising a common gate arrangement having an output, and inputs connected to the outputs of the individual gate arrangements, the common gate arrangement being arranged to provide an output of a first type when the inputs are all of the same type, and otherwise provide an output of a second type.
摘要翻译： 用于测试集成电路的设备，所述集成电路包括通过公共字线连接的多个半导体存储器单元，每个存储器单元包括：交叉耦合排列的相应第一和第二晶体管以形成双稳态锁存器， 第一晶体管代表用于存储高电位或低电位状态的相应第一节点，并连接到相应的第一半导体装置，用于替换从第一节点泄漏的电荷并连接到相应的第一开关装置，可由公共字线激活， 用于将相应的第一节点耦合到相应的第一位线，第二晶体管的漏极表示相应的第二节点，用于存储高电位或低电位状态并连接到相应的第二半导体装置，用于替换从相应的第二位线泄漏的电荷 节点并连接到相应的第二交换装置，可由com激活 单字线，用于将第二节点耦合到相应的第二位线; 以及各自的具有输出端的单独的栅极布置，以及连接到相应的第一和第二位线的输入端，并且当相应的第一和第二位线都处于低电位范围内时，布置成提供第一类型的输出， 否则提供第二类型的输出; 并且该设备包括具有输出的共栅极布置和连接到各个栅极布置的输出的输入端，共同的栅极布置被设置为当输入都是相同类型时提供第一类型的输出，否则 提供第二种输出。
-
公开(公告)号：EP1280056A1
公开(公告)日：2003-01-29
申请号：EP01306398.7
申请日：2001-07-26
发明人： Bowers, Antony , Shann, Richard
CPC分类号： G06F8/54
摘要： Call frame information is used by debugging software. It records how to restore the parent stack frame at any point during execution of a program. It is normally generated during compilation and stored in the executable in a compressed format, consisting of sequences of instructions that describe how the current call frame changes during execution of each function. Described herein is a means of generating call frame information at link time, using linker macro calls generated by a small set of assembler macros.
摘要翻译： 呼叫帧信息由调试软件使用。 它记录了在执行程序期间的任何时候如何恢复父堆栈帧。 它通常在编译期间生成并以压缩格式存储在可执行文件中，该格式由描述当前调用帧在每个功能执行期间如何改变的指令序列组成。 这里描述的是使用由一组汇编器宏生成的链接器宏调用在链接时产生呼叫帧信息的手段。
-
公开(公告)号：EP1257119A1
公开(公告)日：2002-11-13
申请号：EP01303461.6
申请日：2001-04-12
发明人： Lewis, David , Gurney, Howard
CPC分类号： H04N21/4383 , H04N21/42646 , H04N21/42661 , H04N21/42669 , H04N21/42692 , H04N21/434 , H04N21/44004
摘要： A system comprising first input means for receiving a transport stream from an external source, second input means for receiving an input from a memory, means for connecting the first and second input means to an interface which is arranged to provide an output stream to a decoder. The second input means is arranged to provide an output to the interface in such a form that the interface does not distinguish between the output from the first and second input means.
摘要翻译： 一种系统，包括用于从外部源接收传输流的第一输入装置，用于从存储器接收输入的第二输入装置，用于将第一和第二输入装置连接到被配置为向解码器提供输出流的接口的装置 。 第二输入装置被布置成以这样的形式向接口提供输出，使得接口不区分来自第一和第二输入装置的输出。
-
公开(公告)号：EP1255227A1
公开(公告)日：2002-11-06
申请号：EP01303889.8
申请日：2001-04-27
IPC分类号： G06T15/00
CPC分类号： G06T15/005
摘要： A graphic processor having an index processing unit for pre-processing a list of vertices making up a three-dimensional image. The method of pre-processing comprising the following steps. Firstly, decomposing the three-dimensional image into a plurality of primitive elements each defined by a set of vertices, each vertex comprising vertex information stored in a vertex storage area and addressable by a vertex index. Then receiving said vertex indices and creating a set of unique indices identifying a batch of vertices and loading only the vertices corresponding to said unique indices into the vertex storage area. Finally creating transformed primitive elements from transformed vertex information addressed in the vertex storage area using the unique indices.
摘要翻译： 一种具有索引处理单元的图形处理器，用于预处理构成三维图像的顶点列表。 预处理的方法包括以下步骤。 首先，将三维图像分解为由一组顶点定义的多个图元，每个顶点包含存储在顶点存储区域中并且可由顶点索引寻址的顶点信息。 然后接收所述顶点索引并创建一组唯一的索引，该索引标识一批顶点，并仅将对应于所述唯一索引的顶点加载到顶点存储区域中。 最后使用独特的索引从顶点存储区域中寻址的变换顶点信息创建变换的原始元素。
-
公开(公告)号：EP1244214A1
公开(公告)日：2002-09-25
申请号：EP01302735.4
申请日：2001-03-23
发明人： Dellow, Andrew
CPC分类号： H03K23/68 , H03K23/546
摘要： A digital frequency divider includes phase control of the output signal in increments of whole or half cycles of the input frequency. Whole cycle phase control is achieved by varying (logically or physically) the tap off point of a shift register loaded with a bit pattern for appropriate division. Half cycle phase changes is achieved by a multiplexer selecting one of two signals every half cycle.
摘要翻译： 数字分频器包括以输入频率的整个或半个周期为增量的输出信号的相位控制。 通过改变（逻辑上或物理上）通过加载位模式的移位寄存器的抽头点进行适当划分来实现整个周期相位控制。 半周期相位变化通过多路复用器每半周期选择两个信号之一来实现。
-
公开(公告)号：EP1241873A1
公开(公告)日：2002-09-18
申请号：EP01302425.2
申请日：2001-03-15
CPC分类号： H04N21/462 , H04N5/76 , H04N5/913 , H04N21/4334 , H04N21/434 , H04N21/4408 , H04N2005/91364
摘要： For a packet identification (PID) contained at a variable possible location which comprises part only of a 32-bit packet header, a corresponding DES key value is located. A table (10) stored in memory contains for each DES key (12) (i) a packet header (14) comprising 32 bits with a possible PID of e.g. 12, 9 or 8 bits contained at a defined location and with zero values elsewhere, and (ii) a mask value (16) also comprising 32 bits with ones contained at the said defined location of the PID and zeros elsewhere. The table is divided into regions (18) for respective packet format types. An incoming packet header at an input (22) is combined (26) with a first one of the mask values from the table so as to provide a combined value which consists of the value held in the input packet header at the defined location and zeros elsewhere. This combined value is compared (36) with the corresponding packet header stored in the table. If they are not equal, the combining and comparison is repeated for the next row of the table. If they are equal, the corresponding DES key value is read (32) from the table and provided as an output (38). The system can cope with variable PID formats within the packet header without alteration to the hardware but merely with re-programming of the table contents.
摘要翻译： 对于包含在仅包括32位分组报头的部分的可变可能位置处的分组标识（PID），定位相应的DES密钥值。 存储在存储器中的表格（10）包含用于每个DES密钥（12）（i）包括具有例如可能的PID的32位的分组头部（14）。 12,9或8位包含在定义的位置并且在其他位置处具有零值，以及（ii）掩码值（16），其还包括32位，其中包含在PID的所述定义位置处的零位和其它位置处的零。 该表被分成用于相应分组格式类型的区域（18）。 在输入端（22）处的输入分组报头与来自表格的掩码值中的第一个组合（26），以便提供组合值，该组合值由保存在所定义的位置和零的输入分组报头中的值组成 别处。 将该组合值与存储在表中的相应分组报头进行比较（36）。 如果它们不相等，则对于表的下一行重复组合和比较。 如果它们相等，则从表中读取（32）相应的DES密钥值作为输出（38）。 该系统可以处理数据包报头中的可变PID格式，而不会改变硬件，但只能对表内容进行重新编程。
-
公开(公告)号：EP1235471A1
公开(公告)日：2002-08-28
申请号：EP01301786.8
申请日：2001-02-27
发明人： Evans, Paul
IPC分类号： H05K1/14
CPC分类号： H01R12/523 , H05K1/144
摘要： A stackable module for a processor system is described. The module comprises a support plate with a set of topside circuit components mounted to its topside, and topside and underside connectors. The module can be stacked with other such modules and are provided with conductive tracks which are arranged to convey transport stream data and transport stream control signals between modules in a stack. The invention also provides a stack of such modules in a processor system.
摘要翻译： 描述了用于处理器系统的可堆叠模块。 模块包括具有安装到其顶侧的一组顶侧电路部件的支撑板以及顶侧和下侧连接器。 该模块可以与其它这样的模块堆叠并且设置有导电轨道，其被布置成在堆叠中的模块之间传送传输流数据和传输流控制信号。 本发明还在处理器系统中提供这样的模块的堆叠。
-
18.发明公开A method of distinguishing bidirectional pins 审中-公开Verfahren zur Erkennung von bidirektionnellem Anschlussstift
公开(公告)号：EP1096396A1
公开(公告)日：2001-05-02
申请号：EP00309135.2
申请日：2000-10-17
发明人： Ballam, Peter
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method is described for distinguishing between an input or output signal on a bi-directional pin of a model of a hardware circuit. The method comprises the steps of for a bi-directional pin of said model applying signals to said pin at a reduced drive strength such that a driven signal on said pin will be superimposed over the applied signal, and comparing the drive strength on the bi-directional pin and responsive to said comparison determining whether the bi-directional pin is an input or output.
摘要翻译： 描述了用于区分硬件电路模型的双向引脚上的输入或输出信号的方法。 该方法包括以下步骤：所述模型的双向引脚以降低的驱动强度将信号施加到所述引脚，使得所述引脚上的驱动信号将叠加在所施加的信号上，并且比较双向引脚上的驱动强度， 并且响应于所述比较确定双向引脚是输入还是输出。
-
公开(公告)号：EP1079526A1
公开(公告)日：2001-02-28
申请号：EP00303979.9
申请日：2000-05-11
IPC分类号： H03K19/0948 , H03K19/017
CPC分类号： H03K19/01707 , H03K19/0948
摘要： A ratio logic gate has a current mirror (20) controlled by the pull-down transistors (10-13) and supplying a half size pull-down transistor (23). When one or more of the input pull-down transistors (10-13) is on, the mirror current overcomes the output pull-down transistor (23) to provide a high potential output. Process tolerances between p and n type devices is thus avoided.
摘要翻译： 比率逻辑门具有由下拉晶体管（10-13）控制并提供半尺寸下拉晶体管（23）的电流镜（20）。 当一个或多个输入下拉晶体管（10-13）导通时，镜电流克服输出下拉晶体管（23）以提供高电位输出。 因此避免了p型和n型器件之间的工艺公差。
-
公开(公告)号：EP1079524A1
公开(公告)日：2001-02-28
申请号：EP00303948.4
申请日：2000-05-10
IPC分类号： H03K3/356 , H03K19/0185
CPC分类号： H03K3/356121 , H03K3/356191
摘要： A flip-flop circuit comprises a pair of cross-coupled inverters, each of which has a respective FET connected in series between it and the reference terminal, each inverter driving a transistor of an output inverter.
摘要翻译： 触发器电路包括一对交叉耦合的反相器，每个反相器具有串联连接在其与参考端子之间的相应FET，每个反相器驱动输出反相器的晶体管。
-
-
-
-
-
-
-
-
-
搜索结果
90 条记录 (耗时 0.026 秒)
