公开(公告)号：EP1025479A1

公开(公告)日：2000-08-09

申请号：EP98955132.0

申请日：1998-10-26

申请人： CREDENCE SYSTEMS CORPORATION

发明人： ARKIN, Brian, J. ,  GILLETTE, Gary, C. ,  SCOTT, David

IPC分类号： G06F1/00

CPC分类号： G01R31/31813 ,  G01R31/31921

摘要： A parallel processing pattern generation system for an integrated circuit tester includes two pattern memories (PM2, PM3), a main pattern generator (PG1), and two auxiliary pattern generators (PG2, PG3). Each pattern memory may receive and store data patterns from a host computer (24) before the test. All three pattern generators may produce data pattern sequences in a variety of ways by executing separately stored algorithmic programs. The pattern sequences generated by each of the two auxiliary pattern generators separately address the two pattern memories so that either one or both of the two pattern memories may read out pattern data during a test. The main pattern generator includes a routing circuit (30) for receiving as inputs a portion of the pattern data generated by the main pattern generator itself and the pattern data read out of the two pattern memories. The routing circuit, controlled by another portion of the pattern data produced by the main pattern generator, selects from among its inputs on a bit-by-bit, cycle-by-cycle basis to provide pattern data for controlling tester activities during each cycle of a test.

公开(公告)号：EP1021861A2

公开(公告)日：2000-07-26

申请号：EP98925174.9

申请日：1998-06-02

申请人： CREDENCE SYSTEMS CORPORATION

发明人： ARKIN, Brian, J.

IPC分类号： H03H11/26

CPC分类号： H03K5/135 ,  H03K5/131 ,  H03K2005/00071

摘要： A programmable delay circuit (10) produces an OUTPUT signal following an INPUT signal with a delay selected by input delay selection data. The delay circuit includes a tapped delay line, a multiplexer, a delay adjustment stage and a programmable encoder. The delay line (12) includes a set of N delay elements connected in series for successively delaying the INPUT (12) signal to produce a set of N output TAP signals. The multiplexer passes a selected TAP signal to the delay adjustment stage (22). The delay adjustment stage delays the selected TAP signal to produce the OUTPUT signal. The programmable encoder (38) encodes the input delay selection data to provide signals for controlling the multiplexer and for adjusting the delay of the delay adjustment stage. The manner in which the encoder encodes each separate delay selection data value is adjustable so that each of the N selectable delays can be separately calibrated.

公开(公告)号：EP1015900A1

公开(公告)日：2000-07-05

申请号：EP98942174.8

申请日：1998-08-20

申请人： CREDENCE SYSTEMS CORPORATION

发明人： ARKIN, Brian, J.

IPC分类号： G01R31/28

CPC分类号： G01R31/31922

摘要： An integrated circuit tester includes a pattern generator (22), a main and an auxiliary period generator (20(1), 20(2)), and set of tester channels (CH(1)...CH(N)), one for each terminal of an integrated circuit device under test (DUT). A test is organized into a succession of main test cycles, each divided into two or more auxiliary test cycles. The main period generator (20(1)) indicates the start of each main test cycle and the auxiliary period generator (20(2)) indicates the start of each auxiliary test cycle. Each tester channel is programmed to respond either to the main period generator or to the auxiliary period generator. At the start of each main test cycle, the pattern generator supplies data to each tester channel indicating a test activity to be carried out at the DUT terminal and indicates a time relative to a start of a test cycle at which the activity is to be carried out. Each tester channel programmed to respond to the main period generator carries out the indicated test activity once at the indicated time during the main test cycle. Each tester channel programmed to respond to the auxiliary period generator repeats the indicated test activity at the indicated time during each successive auxiliary test cycle spanned by the main test cycle.

公开(公告)号：EP0979415A1

公开(公告)日：2000-02-16

申请号：EP98918921.2

申请日：1998-04-30

申请人： CREDENCE SYSTEMS CORPORATION

发明人： KHATER, Nabil ,  BAKER, David, A.

IPC分类号： G01R31/02

CPC分类号： G01R1/06705

摘要： A tester includes a manipulator (200) attached to a test head (1) for testing semiconductor devices having a range of motion in mutiple degrees of freedom. Vertical (500) and horizontal (600) bearing assemblies, an expansion joint (400), a swing arm (40), a tumble assembly (700) coupled by a rotary bearing assembly (300) to the swing arm provide for lateral movement of the test head in three dimensions as well as angular movement of the test head in horizontal, tumble or twist rotations.

摘要翻译： 测试器包括附接到测试头（1）的操纵器（200），用于测试具有多个自由度范围的运动的半导体器件。 通过旋转轴承组件（300）联接到摆臂的竖直（500）和水平（600）轴承组件，膨胀接头（400），摆臂（40），翻转组件（700）提供 三维测试头以及测试头在水平，翻滚或扭曲旋转中的角运动。

公开(公告)号：EP0872070A1

公开(公告)日：1998-10-21

申请号：EP96943787.0

申请日：1996-12-17

申请人： CREDENCE SYSTEMS CORPORATION

发明人： MILLER, Charles, A.

IPC分类号： H04L7 ,  G01R31 ,  G06F1 ,  H03L7 ,  H04J3

CPC分类号： H03L7/0812 ,  G01R31/31922 ,  G06F1/10 ,  H03L7/07 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/0041

摘要： A clock signal distribution system provides a set of synchronized, spatially distributed local clock signals (CLKL). The system includes a source of periodic reference clock signal (CLK), a set of spatially distributed deskewing circuits (12) and first and second transmission lines (18 and 20). The first transmission line routes the reference clock signal from the source (14) to the deskewing circuits in a first order of succession. The second transmission line routes the reference clock signal from the source to the deskewing circuits in a second order of succession that is reverse to the first order of succession. The two transmission lines are of similar length and velocity of signal propagation between adjacent deskewing circuits. Each deskewing circuit produces an output local clock signal having a phase that is midway between phases of the clock signal arriving at the deskewing circuit via the first and second transmission lines. The local ouput signals produced by the deskewing circuits all have the same phase and frequency despite varying distances of the deskewing circuits from the clock source.

公开(公告)号：EP0852730A1

公开(公告)日：1998-07-15

申请号：EP96930872.0

申请日：1996-09-10

申请人： CREDENCE SYSTEMS CORPORATION

发明人： LESMEISTER, Gary, J.

IPC分类号： G01R31 ,  G06F1

CPC分类号： G01R31/31813 ,  G01R31/2851 ,  G01R31/31907 ,  G01R31/3191 ,  G01R31/31921 ,  G01R31/31922 ,  G06F1/025 ,  G06F1/04

摘要： An integrated circuit tester includes several processing nodes, one node associated with each terminal of an integrated circuit device under test (DUT). At precisely determined times, each node generates and transmits a test signal to the associated DUT terminal or samples a DUT output signal produced at the DUT terminal. Each node includes memory for storing algorithmic instructions for generating a set of commands indicating when a test signal is to be transmitted to the associated terminal and indicating when a DUT output at the associated node is to be sampled. Each node also includes a processor for processing the algorithmic instructions to produce the commands. Each node further includes circuits responsive to the commands for transmitting the test signals to the associated DUT terminal and for sampling the DUT output signal produced at the associated DUT terminal at times indicated by the commands. The processing nodes are interconnected in serial fashion to form a network for conveying the algorithmic instructions to the memory of each node and for conveying signals for synchronizing operations of the processing nodes. The nodes contain circuitry to start and stop operations in a unified manner so that the serially connected nodes act as if connected in parallel.

公开(公告)号：EP0653072A1

公开(公告)日：1995-05-17

申请号：EP93918395.0

申请日：1993-07-26

申请人： CREDENCE SYSTEMS CORPORATION

发明人： DINTEMAN, Bryan, J.

IPC分类号： G01R31

CPC分类号： G01R31/31922 ,  G01R31/2834

摘要： Apparatus for testing an integrated circuit device (DUT) having an input port and an output port comprises multiple state devices (10-16) each having multiple states that occur in a predetermined sequence and an output port at which it provides an event signal. A first of the state device is an emitting device (10) that emits an event marker signal at a predetermined time in advance of entering a predefined state, a second of the state devices is a receiving device (11) that responds to receipt of an event marker signal, at least one of the state devices (11) has its output port connected to the input port of the DUT, and at least one of the state devices is a measurement device (13) connected to the output port of the DUT. An interconnection matrix (30) is connected to each state device and allows each state device to communicate an event marker signal to each other.

公开(公告)号：EP1466194B1

公开(公告)日：2007-04-04

申请号：EP02806615.7

申请日：2002-12-11

申请人： CREDENCE SYSTEMS CORPORATION

发明人： Nader, Pakdaman ,  Vickers, James S.

IPC分类号： G02B3/00

CPC分类号： G11B7/122 ,  B82Y10/00 ,  G02B3/00 ,  G02B3/02 ,  G11B7/1374 ,  G11B7/1378 ,  G11B7/1387 ,  G11B2007/13727 ,  H01L27/14625

摘要： A bi-convex solid immersion lens is disclosed. Unlike conventional plano-convex solid immersion lenses having a flat bottom surface, the disclosed lens has a convex bottom surface. The radius of curvature of the bottom surface is smaller than that of the object to be inspected. This construction allows for a more accurate determination of the location of the inspected feature, and enhances coupling of light between the immersion lens and the inspected object. The disclosed lens is particularly useful for use in microscope for inspection of semiconductor devices and, especially flip-chip (or chip scale) packaged devices. The immersion lens can also be incorporated in a read or read/write head of optical memory media.

公开(公告)号：EP1726968A2

公开(公告)日：2006-11-29

申请号：EP06010975.8

申请日：2006-05-29

申请人： CREDENCE SYSTEMS CORPORATION

发明人： Portune, Richard A.

IPC分类号： G01R31/28 ,  H01L21/02 ,  G01N1/32

CPC分类号： G01N1/32 ,  G01R31/2898 ,  Y10S438/977

摘要： A method is provided for preparing a semiconductor wafer (500) for testing. The method includes selecting a die (525) to be tested; measuring a diagonal of the die; thinning an area (550) over the die extending beyond the scribe lines (520a,520b), the thinned area may be a circular area having a diameter that is larger than the measured diagonal; providing an insert (560) inside the thinned area; and providing an adhesive (580) on the peripheral area of the insert so as not to obscure the optical path to the die. The insert (560) is advantageously made of an undoped silicon.

摘要翻译： 提供了一种用于制备用于测试的半导体晶片（500）的方法。 该方法包括选择待测试的管芯（525）; 测量模具的对角线; 使在模具上方延伸超过划线（520a，520b）的区域（550）变薄，所述变薄区域可以是直径大于测量对角线的圆形区域; 在所述减薄区域内提供插入件（560）; 以及在所述插入件的周边区域上提供粘合剂（580），以便不会模糊到所述模具的光路。 插入件（560）有利地由未掺杂的硅制成。

公开(公告)号：EP1450172B1

公开(公告)日：2005-12-28

申请号：EP04009371.8

申请日：1998-08-20

申请人： CREDENCE SYSTEMS CORPORATION

发明人： Gillette, Garry

IPC分类号： G01R31/319 ,  G01R31/28 ,  G05F1/56

CPC分类号： G01R31/3004 ,  G01R31/2841 ,  G01R31/2879 ,  G01R31/31924