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公开(公告)号：EP0220816A2
公开(公告)日：1987-05-06
申请号：EP86306965.4
申请日：1986-09-10
发明人： Austin, Kenneth
IPC分类号： H03K17/687
CPC分类号： H03K19/1778 , G06F17/5027 , H03K5/026 , H03K17/687 , H03K19/1733 , H03K19/1736 , H03K19/17704
摘要： A gated binary signal transmission circuit in a field effect semiconductor chip comprises a single signal-pass transistor (20A, B) connected between a bit signal input (28A, B) to one of its electrodes (24A, B) and a bit signal output (12A, B) from another of its electrodes (26A, B). Its control electrode (22A, B) is connected for temporary energisations by switching circuitry (32,34) operative only at prescribed intervals, the single signal-pass transistor (20A, B) being operative to pass signals between such energisations of its control electrode (22A, B). Conduction of the single signal-pass transistor between energisations will persist, though with some decay, due to inherent capacitance and the control electrode being left "floating" between energisations.
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公开(公告)号：EP0776093A2
公开(公告)日：1997-05-28
申请号：EP97101407.1
申请日：1994-06-01
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/1736 , H03K19/17704 , H03K19/1774 , H03K19/17744 , H03K19/17796
摘要： A configurable semi-conductor integrated circuit comprising an area thereof formed with a plurality of logic circuits at discrete sites or cells (cc) respectively defining a matrix array of cells. The matrix array of cells is subdivided at least into zones (each comprising a matrix array of cells) and further comprising a porting arrangement for each zone and a hierarchical routing resource structure comprising:-
(i) global connection parts (G, X) having selectable connections with the porting arrangement of each zone,
(ii) medium connection parts (M) extending from the porting arrangement and selectably connectable with at least some of the cells in a zone, and
(iii) local direct connection paths comprising a restricted signal translation system.
The application also describes a configurable semi-conductor integrated circuit comprising a matrix array of core cells (cc), each of the cells having a first simple function in common and at least one subsidiary function, there being at least two different subsidiary functions, the core cells being grouped in tiles comprising a matrix array of the core cells smaller than the whole array and wherein each tile has at least one of each different subsidiary functions and wherein the tiles of core cells are arranged so as to uniformly cover the array. Preferably there are fours cells to a tile and the preferred subsidiary function are:- wired-OR, XOR, D-type flip flop and latch function.
The above features are preferably combined to produce a particularly advantageous construction of configurable semi-conductor integrated circuit.摘要翻译： 可配置半导体集成电路包括核心单元（cc）的矩阵阵列，每个单元具有共同的第一简单功能和至少一个辅助功能，存在至少两个不同的辅助功能，核心单元被分组 在包括小于整个阵列的核心单元的矩阵阵列的瓦片中，并且其中每个瓦片具有每个不同的辅助功能中的至少一个，并且其中核心单元的瓦片被布置成均匀地覆盖阵列。 优选地，有四个单元格到瓦片，并且优选的辅助功能是： - 线或或XOR，D型触发器和锁存功能。
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公开(公告)号：EP0630115A2
公开(公告)日：1994-12-21
申请号：EP94303952.9
申请日：1994-06-01
IPC分类号： H03K19/177 , H03K19/173
CPC分类号： H03K19/17736 , H03K19/1736 , H03K19/17704 , H03K19/1774 , H03K19/17744 , H03K19/17796
摘要： A configurable semi-conductor integrated circuit comprising an area thereof formed with a plurality of logic circuits at discrete sites or cells (cc) respectively defining a matrix array of cells. The matrix array of cells is subdivided at least into zones comprising a porting arrangement for each zone and a hierarchical routing resource structure comprising:-
(i) global connection parts (G,X) having selectable connections with the porting arrangement of each zone,
(ii) medium connection parts (M) extending from the porting arrangement and selectably connectable with at least some of the cells in a zone, and
(iii) local direct connection paths comprising a restricted signal translation system.
The application also describes a configurable semi-conductor integrated circuit comprising a matrix array of core cells (cc), each of the cells having a first simple function in common and at least one subsidiary function, there being at least two different subsidiary functions, the core cells being grouped in tiles comprising a matrix array of the core cells smaller than the whole array and wherein each tile has at least one of each different subsidiary functions and wherein the tiles of core cells are arranged so as to uniformly cover the array. Preferably there are fours cells to a tile and the preferred subsidiary function are:- wired-OR, XOR, D-type flip flop and latch function.摘要翻译： 一种可配置的半导体集成电路，其包括在分立位置或多个单元（cc）处形成有多个逻辑电路的区域，所述多个逻辑电路分别限定单元阵列阵列。 小区的矩阵阵列至少细分为包括每个区域的移植装置的区域和分层路由资源结构，包括： - （i）具有与每个区域的移植布置的可选连接的全局连接部分（G，X） ii）从移动装置延伸的中间连接部分（M），并且可选地可与区域中的至少一些小区连接，以及（iii）包括受限信号转换系统的本地直接连接路径。 该应用还描述了一种可配置的半导体集成电路，其包括核心单元（cc）的矩阵阵列，每个单元具有共同的第一简单功能和至少一个辅助功能，其中至少有两个不同的辅助功能， 核心单元被分组在包括小于整个阵列的核心单元的矩阵阵列的瓦片中，并且其中每个瓦片具有每个不同的辅助功能中的至少一个，并且其中核心单元的瓦片被布置成均匀地覆盖阵列。 优选地，有四个单元格到瓦片，并且优选的辅助功能是： - 线或或XOR，D型触发器和锁存功能。
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公开(公告)号：EP0611165A1
公开(公告)日：1994-08-17
申请号：EP94301005.8
申请日：1994-02-11
IPC分类号： H03H19/00
CPC分类号： H03H19/00
摘要： A switched capacitor circuit is described which is programmable so that its function can be set by a user. Thus, control circuitry and selection circuitry are provided to enable one of a plurality of alternative control signals to be provided to switch circuits of the switched capacitor circuit. In this way, the function of the switched capacitor circuits can be altered. Where there are a plurality of switched capacitor circuits connected in an array, the topology of the array can be altered by suitably routing particular input signals to particular outputs by selecting the control signals to control the switched circuits. A field programmable array of this type is also described.
摘要翻译： 描述了可编程的开关电容器电路，使得其功能可以由用户设置。 因此，提供控制电路和选择电路以使多个替代控制信号之一能够提供给开关电容器电路的开关电路。 以这种方式，可以改变开关电容器电路的功能。 在存在阵列连接的多个开关电容器电路的情况下，通过选择控制信号来控制开关电路，可以改变将特定输入信号适当地路由到特定输出的阵列拓扑。 还描述了这种类型的现场可编程阵列。
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15.发明公开Electronic identification system with anti-tampering protection 失效Elektronisches Identifizierungssystem mit Einbruchschutz。
公开(公告)号：EP0586192A1
公开(公告)日：1994-03-09
申请号：EP93306766.2
申请日：1993-08-25
发明人： Austin, Kenneth
IPC分类号： B60R25/00 , B60R25/10 , G08G1/017 , G08B13/186
CPC分类号： G08G1/017 , B60R25/00 , B60R25/1018
摘要： An electronic identity device is proposed for securing to equipment, especially a vehicle, and has anti-tampering protection. The device is intended to prevent the identity of a vehicle being changed unknowingly. The device comprises at least a control processor (10) having a memory containing accessible data unique to the equipment (for example a vehicle chassis number and/or engine number), and preferably a slave processor (20). The device also comprises means (1, 7, 8) generating a security signal and means for detecting any lack of integrity of the security signal to generate a tamper warning signal. The security signal is generated repeatedly irrespective of whether the vehicle is in operation. More particularly, the security signal is transmitted over a communication link (18) in the form of fibre optic cabling which is adhered to the equipment. Any attempt to remove the electronic device or tamper with the cabling will corrupt the security signal and therefore generate a tamper warning signal.
摘要翻译： 提出了一种电子身份识别装置，用于固定到设备，特别是车辆上，并具有防篡改保护。 该装置旨在防止车辆的身份在不知不觉中改变。 该设备至少包括控制处理器（10），其具有包含设备唯一的可访问数据的存储器（例如车辆底盘编号和/或发动机编号），并且优选地为从属处理器（20）。 该装置还包括产生安全信号的装置（1,7,8）和用于检测安全信号的完整性的任何缺乏以产生窜改警告信号的装置。 无论车辆是否在运行，重新产生安全信号。 更具体地，安全信号通过粘附到设备上的光纤电缆形式的通信链路（18）传输。 任何删除电子设备或篡改电缆的尝试都会破坏安全信号，从而产生篡改警告信号。
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公开(公告)号：EP0450863A3
公开(公告)日：1992-08-05
申请号：EP91302724.9
申请日：1991-03-27
发明人： Austin, Kenneth
IPC分类号： G11C27/02
CPC分类号： G11C27/024 , G11C27/00 , G11C27/026
摘要： This invention relates to semiconductor integrated circuits which find utility in analogue systems. An integrated circuit of the invention comprises an array (A) of configurable analogue cells (CL) each of which is capable of interconnection with other cells in the array by means of an interconnection network (HB, VB). Each of the cells can be selectively and individually selected by means of select signals (SS) and (DD) emanating from shift registers (DSRH, PSRV). When selected the cell (CL) may be configured with configuration data (DD, AD) which both sets the cell to take up a particular electrical configuration by means of digital data (DD) and sets various programmable resistors and capacitors (P/res, P/cap) in the cells to particular values by means of analogue signals (AD). The configuration data is held in a random access memory RAM. Some of this data is converted to analogue form (AD) by means of a ditigal-to-analogue converter (DAC). The circuit is controlled by a central control (CC) and is capable of being configured to implement particular analogue functional applications from a plurality of possible analogue functional applications. Provision in the circuitry is made to automatically compensate for manufacturing component tolerances.
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公开(公告)号：EP0260033A2
公开(公告)日：1988-03-16
申请号：EP87307599.8
申请日：1987-08-27
发明人： Austin, Kenneth
IPC分类号： H03K17/60 , H03K19/173
CPC分类号： H03K17/602 , H03K19/1736
摘要： Selectable signal connection provisions (30 or 50) are made for passing signals relative to logic circuitry of digital bipolar semiconductor integrated circuits. Each such provision (30 or 50) has formed on the chip for each selectable signal connection, an active circuit element (22 or 42) whose conduction state relative to signals concerned is controlled by applied circuit conditions. The conditions are selected by operative control circuitry (32 or 52) responsive to a configuring or selection signal (at 34 or 54) applied temporarily thereto for switching between stable states and thus determining the conduction state of the active circuit element (22 or 42)
摘要翻译： 可选择的信号连接规定（30或50）用于相对于数字双极半导体集成电路的逻辑电路传递信号。 每个这样的设备（30或50）已经在每个可选择的信号连接的芯片上形成，其相对于相关信号的导通状态由施加的电路条件控制的有源电路元件（22或42）。 响应于暂时施加的配置或选择信号（在34或54），在操作控制电路（32或52）之间切换条件，以便在稳定状态之间切换，从而确定有源电路元件（22或42）的导通状态，
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公开(公告)号：EP0450863B1
公开(公告)日：1996-07-10
申请号：EP91302724.9
申请日：1991-03-27
发明人： Austin, Kenneth
IPC分类号： G11C27/02
CPC分类号： G11C27/024 , G11C27/00 , G11C27/026
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公开(公告)号：EP0372749A3
公开(公告)日：1990-08-01
申请号：EP89312115.2
申请日：1989-11-22
IPC分类号： H03K19/173
CPC分类号： H03K19/17792 , H03K19/173 , H03K19/17704 , H03K19/17728
摘要： This invention is concerned with semiconductor integrated circuits of the type comprising configurable logic circuit arrays of the type disclosed in specification No. GB B-2180382. Such an array may be programmed to configure a plurality of NAND-gates (G1) in the array to perform various and different logic functions. This invention is particularly concerned with the provision of an additional logic circuit (c) at each discrete site or cell which additional logic circuit (c) is controllable by a control means (GCS) to cause the additional logic circuit (c) and the logic circuit to operate as either a simple NAND logic function or a simple LATCH logic function.
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公开(公告)号：EP0219221A2
公开(公告)日：1987-04-22
申请号：EP86306966.2
申请日：1986-09-10
发明人： Austin, Kenneth
IPC分类号： H03K19/177
CPC分类号： H03K19/17748 , G06F17/5027 , H03K5/026 , H03K17/687 , H03K19/1733 , H03K19/1736 , H03K19/17704 , H03K19/17736 , H03K19/1778
摘要： Configurable semiconductor integrated circuits as-made each have a plurality of logic circuits formed at discrete sites (10S). For each logic circuit, direct selectably conducting/non- conducting connection paths (14A,B,C,F) extend from its output to input of a first set of other logic circuits and to its inputs from outputs of a second set of other logic circuits. All of the sets for all of the logic circuits are each different. Other direct connection paths (50R,50C) are selectably connectable to inputs (14D,E) and outputs (52G,H) of the logic circuits. Selection can be irreversible (Figure 8) or reversible (Figures 9, 10, 11, 18) and involves coincident signal addressing (22R,C) of the sites (105) and coded configuring ofthe paths at that site. Reversible selection can beviafield effect transistors or bipolar transistors and can be at or near normal logic signal levels and speeds (Figures 11 and 18). Versatile configurable input/output arrangements are described (Figures 13-16), also reconfigurable data processing systems using the reversible transistor provisions (Figures 20-23).
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