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公开(公告)号：EP1811648B1
公开(公告)日：2009-09-02
申请号：EP07090076.6
申请日：2000-05-26
IPC分类号： H03B5/12
CPC分类号： H03B27/00 , H03B5/1209 , H03B5/1228
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公开(公告)号：EP1305883B1
公开(公告)日：2009-02-11
申请号：EP01946379.3
申请日：2001-06-14
发明人： SCHMITT, Andrew , BOGGESS, Tim
CPC分类号： H04L29/06 , H04J3/14 , H04J3/1611 , H04J2203/0051 , H04L69/08
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13.发明公开Fast locking clock and data recovery unit 有权Schnell verriegelnde Takt- undDatenrückgewinnungseinheit
公开(公告)号：EP1555776A1
公开(公告)日：2005-07-20
申请号：EP04090018.5
申请日：2004-01-19
IPC分类号： H04L7/033
CPC分类号： H04L7/0338 , H04L7/046
摘要： Method and apparatus for recovering a clock and/or data from a serial data stream. A snapshot register and decoder using ring decoding decodes an N-bit data sample generated from an N-phase clock to determine a clock phase for extracting data. The ring decoding involves creating a first ring from the oversampled data by cyclically arranging the N-bit data sample in angle positions corresponding to clock phases. A second ring around the first one is calculated by EXNORing the samples of the first ring, subsequent rings are formed by ANDing the samples of the previous rings. The procedure stops when a 0-1-0 sequence appears on a ring. The optimum phase is determined as the phase of the 0-1-0 plus the ring index divided by two.
摘要翻译： 从串行数据流中恢复时钟和/或数据的方法和装置。 使用环形解码的快照寄存器和解码器解码从N相时钟产生的N位数据样本，以确定提取数据的时钟相位。 环形解码涉及通过将N位数据样本循环地布置在对应于时钟相位的角度位置中，从过采样数据产生第一环。 第一个环周围的第二个环是通过排除第一个环的样品来计算的，随后的环由前一个环的样品进行AND运算而形成。 当环上出现0-1-0序列时，程序停止。 确定最佳相位为0-1-0加上环指数除以2的相位。
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公开(公告)号：EP1239595A3
公开(公告)日：2004-02-11
申请号：EP02090104.7
申请日：2002-03-11
发明人： Onvural, O. Raif , Mudoi, Uday
CPC分类号： H03M13/091 , H03M13/15
摘要： A method and apparatus for detecting errors in a data packet being transmitted as a set of smaller data cells by performing operations on the Cyclic Redundancy Check (CRC) values of the individual cells. An error detection apparatus initializes a memory area with a first value. The apparatus generates a CRC value for a first data cell. The apparatus combines the first value and the CRC value for the first cell in a XOR operation and the apparatus stores the result in a memory location. For subsequent cells in the data packet, the apparatus generates a cell CRC value, shifts the value in the memory location twelve times, and replaces the shifted value in the memory location with a new value generated from a XOR operation performed on the shifted value and the cell CRC value. The apparatus compares the final value in the memory location with an end comparison value and generates an error signal if the final and comparison values are different.
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15.发明公开
公开(公告)号：EP1257099A2
公开(公告)日：2002-11-13
申请号：EP02090163.3
申请日：2002-05-03
发明人： Vu, Chuong D.
CPC分类号： H04L49/1576 , H04L49/30 , H04L49/50 , H04L2012/568
摘要： A load balancing system and method for network nodes is provided. The load balancing system includes crossbar devices, queues to receive data and a load balancer. The load balancer determines the amount of data in each of the queues and sends data to specific crossbar devices based on the amount of data in each queue. The queues include a high priority queue and a number of non-high priority queues.
摘要翻译： 提供了网络节点的负载均衡系统和方法。 负载均衡系统包括交叉设备，接收数据的队列和负载均衡器。 负载平衡器根据每个队列中的数据量确定每个队列中的数据量并将数据发送到特定的交叉开关设备。 队列包括高优先级队列和多个非高优先级队列。
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16.发明公开
公开(公告)号：EP1202451A2
公开(公告)日：2002-05-02
申请号：EP01250354.6
申请日：2001-10-11
发明人： Bergman, Dave , McDonald, Jim , HU, Yaqi , Tan, Kok-Lean
IPC分类号： H03H7/38
CPC分类号： H05K1/0246 , H03H7/38 , H05K2201/10022 , H05K2201/1053 , H05K2201/10689
摘要： Methods and apparatus for providing precision on-chip termination of transmission lines are provided which enable the termination of transmission lines using on-chip resistors configured into networks, which have resistances related to the resistance of an external reference resistor. The external reference resistor is used to configure an on-chip reference resistor network so that it has a resistance related to the resistance of the external reference resistor. Termination resister networks are then configured so that their resistances bear a predetermined relationship to the resistance of the on-chip reference resistor network. In one embodiment the resistance of each of the termination resistor networks is substantially the same as the characteristic impedances of each of the transmission lines.
摘要翻译： 提供了用于提供传输线的精确片上终止的方法和装置，其能够使用配置成网络的片上电阻终止传输线，其具有与外部参考电阻器的电阻相关的电阻。 外部参考电阻用于配置片上参考电阻网络，使其具有与外部参考电阻电阻相关的电阻。 然后将端接电阻网络配置成使得其电阻与片上参考电阻网络的电阻具有预定的关系。 在一个实施例中，每个终端电阻网络的电阻基本上与每个传输线的特征阻抗相同。
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公开(公告)号：EP1118154A2
公开(公告)日：2001-07-25
申请号：EP00937898.5
申请日：2000-05-26
IPC分类号： H03C1/00
CPC分类号： H03B27/00 , H03B5/1209 , H03B5/1228
摘要： An adjustable frequency oscillator with a wide tuning range which can be voltage or current controlled. A maximum tuning per feedback current is obtained by phase shifting a feedback signal by approximately 90 degrees with respect to the oscillating output signal, which is internally generated by the adjustable frequency oscillator. Over the frequency range of operation, the oscillation frequency of the oscillating output signal is linearly controllable. The adjustable frequency oscillator is also implemented as a ring oscillator and/or an oscillator with ranging.
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公开(公告)号：EP1023793A2
公开(公告)日：2000-08-02
申请号：EP99943914.4
申请日：1999-08-25
IPC分类号： H04L7/00
CPC分类号： H04L25/063 , H04L7/0037 , H04L7/033 , H04L7/0334
摘要： A microprocessor (45) controlled data recovery unit with an adjustable sampling and signal comparison level. The data recovery unit includes a data channel (47a) and a monitor channel (47b). The monitor channel samples an incoming data stream in a varying manner. The results of the sampling in the monitor channel are used to adjust the sampling and comparing of the signal in the data channel. The data recovery unit includes a PLL (35) based clock recovery unit in one embodiment, and in another embodiment the clock signal is derived by the microprocessor.
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公开(公告)号：EP2777211A1
公开(公告)日：2014-09-17
申请号：EP12848224.7
申请日：2012-11-07
发明人： BRANSCOMB, Brian
CPC分类号： H04L45/00 , H04J3/0667 , H04J3/0697 , H04L45/74 , H04L47/28 , H04L63/0428 , H04L63/162
摘要： A physical layer device provides both timestamp processing and security processing. The timestamp processing may be PTP processing according to IEEE Std. 1588 and/or OAM processing according to ITU-T Recommendation Y.1731. The security processing may be MACsec processing according to IEEE Std. 802.1AE. The timestamp processing may delay some packets to avoid impairing accuracy of timing information. For example, the accuracy of timing information could be impaired when a packet containing the timing information is delay due to additional bits added to a preceding packet to include a security tag and integrity check value.
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公开(公告)号：EP2351231A2
公开(公告)日：2011-08-03
申请号：EP09826845.1
申请日：2009-11-13
发明人： COE, Tim
CPC分类号： H03M13/2792 , H03M13/15 , H03M13/152 , H03M13/2721 , H03M13/2732 , H03M13/2757 , H03M13/29 , H03M13/3746 , H03M13/6561 , H04L1/0041
摘要： Continuously interleaved codewords are used in a communication system to provide error correction capability. In general, each codeword shares symbols with both preceeding and subsequent codewords, when the codewords are arranged in an order, such that correction of symbols in any one codeword also corrects symbols in another codeword and correction of symbols in any codeword may allow, considering possible corrections of intermediate codewords, for further correction of any codeword in the order of codewords. In one embodiment received information may be arranged in subframes, with each subframe including terminal symbols of a plurality of codewords, each of the plurality of codewords including symbols in multiple subframes.
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