ASSEMBLY STRUCTURE AND ELECTRONIC DEVICE HAVING THE SAME
    1.
    发明公开
    ASSEMBLY STRUCTURE AND ELECTRONIC DEVICE HAVING THE SAME 审中-公开
    安东尼奥斯克里克斯堡(EORKTRONISCHE VORRICHTUNG DAMIT)

    公开(公告)号:EP3110238A3

    公开(公告)日:2017-04-26

    申请号:EP16175340.5

    申请日:2016-06-20

    Abstract: The present disclosure provides an assembly structure for providing power for a chip (22, 62, 102) and an electronic device using the same. The assembly structure includes: a circuit board (21, 61, 101), configured to provide a first power supply; a chip (22, 62, 102); and a first power converting module (23, 63, 103, 69'), configured to electrically connect the circuit board (21, 61, 101) and the chip (22, 62, 102), convert the first power supply to a second power supply, and supply the second power supply to the chip (22, 62, 102), wherein the circuit board (21, 61, 101), the chip (22, 62, 102) and the first power converting module (23, 63, 103, 69') are stacked to form the assembly structure. The present disclosure assembles a power converting module (23, 63, 103) with a circuit board (21, 61, 101) and a chip (22, 62, 102) in a stacking manner, which may shorten a current path between the power converting module (23, 63, 103) and the chip (22, 62, 102), reduce current transmission losses, improve efficiency of a system, reduce space occupancy and save system resource.

    Abstract translation: 本公开提供了一种用于为芯片(22,62,102)提供电力的组装结构和使用其的电子设备。 组装结构包括:电路板(21,61,101),被配置为提供第一电源; 芯片(22,62,102); 和配置成电连接所述电路板(21,61,101)和所述芯片(22,62,102)的第一电力转换模块(23,63,103,69')将所述第一电源转换为第二电源 电源,并将第二电源供应到芯片(22,62,102),其中电路板(21,61,101),芯片(22,62,102)和第一电力转换模块(23) 63,103,69')堆叠以形成组装结构。 本公开以堆叠方式与电路板(21,61,101)和芯片(22,62,102)组装电力转换模块(23,63,103),这可以缩短电力之间的电流路径 转换模块(23,63,103)和芯片(22,62,102),减少电流传输损耗,提高系统效率,减少占用空间并节省系统资源。

    ELECTRICAL ASSEMBLY
    7.
    发明公开
    ELECTRICAL ASSEMBLY 有权
    电气装配

    公开(公告)号:EP2022301A2

    公开(公告)日:2009-02-11

    申请号:EP07797784.1

    申请日:2007-05-25

    Abstract: An electrical assembly including a substantially planar substrate having at least one recess therein and a plurality of electrical components. The electrical components are positioned in the at least one recess and include a first electrical component and a second electrical component. Each of the electrical components has a body and an electrical connection. The electrical connection of the first electrical component and the electrical connection of the second electrical component are aligned with each other when the body of the first electrical component is in a recess and the body of the second electrical component is in a recess.

    Ultra low inductance multi layer ceramic capacitor
    10.
    发明公开
    Ultra low inductance multi layer ceramic capacitor 有权
    非常低的感应多层陶瓷电容器

    公开(公告)号:EP1480236A3

    公开(公告)日:2004-12-01

    申请号:EP04010108.1

    申请日:2004-04-28

    Inventor: Sutardja, Sehat

    Abstract: A multilayer capacitor having a low parasitic inductance includes a plurality of first electrode and a second electrode plates (e.g. 412-418), a dielectric (402-410) , a first contact (420), and a second contact (422). The first electrode (e.g. 412) is substantially rectangular and it includes a first contact finger (430). The dielectric has a first surface and a second surface, wherein the first and second surfaces are situated opposite with each other. The first surface of the dielectric is coupled with the first electrode. The second electrode (e.g. 442) is substantially rectangular and it includes a first contact finger (432). The second electrode is coupled to the second surface of the dielectric. The first contact (420) is coupled to the first contact finger (430) of the first electrode (e.g. 412). The second contact (422) is coupled to the first contact finger (432) of the second electrode (e.g. 442). The second contact is situated at a minimal space (e.g. 442) from the first contact to reduce the parasitic inductance.

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