Abstract:
The present disclosure provides an assembly structure for providing power for a chip (22, 62, 102) and an electronic device using the same. The assembly structure includes: a circuit board (21, 61, 101), configured to provide a first power supply; a chip (22, 62, 102); and a first power converting module (23, 63, 103, 69'), configured to electrically connect the circuit board (21, 61, 101) and the chip (22, 62, 102), convert the first power supply to a second power supply, and supply the second power supply to the chip (22, 62, 102), wherein the circuit board (21, 61, 101), the chip (22, 62, 102) and the first power converting module (23, 63, 103, 69') are stacked to form the assembly structure. The present disclosure assembles a power converting module (23, 63, 103) with a circuit board (21, 61, 101) and a chip (22, 62, 102) in a stacking manner, which may shorten a current path between the power converting module (23, 63, 103) and the chip (22, 62, 102), reduce current transmission losses, improve efficiency of a system, reduce space occupancy and save system resource.
Abstract:
A method of manufacturing a battery module for use in a vehicle is presented. The method may include disposing battery cells into a lower housing and disposing a lid assembly over the battery cells. The lid assembly may include a lid and bus bar interconnects disposed on the lid. The method may also include disposing a printed circuit board (PCB) assembly onto the lid assembly and electrically coupling portions of the lid assembly, portions of the PCB assembly, and the battery cells to each other.
Abstract:
A method of manufacturing a battery module for use in a vehicle is presented. The method may include disposing battery cells into a lower housing and disposing a lid assembly over the battery cells. The lid assembly may include a lid and bus bar interconnects disposed on the lid. The method may also include disposing a printed circuit board (PCB) assembly onto the lid assembly and electrically coupling portions of the lid assembly, portions of the PCB assembly, and the battery cells to each other.
Abstract:
A rechargeable battery pack according to an exemplary embodiment of the present invention includes a plurality of unit cells (11, 12, 13, 14), connection tabs (30, 40) for electrically connecting the plurality of unit cells, connection plates (50, 70) combined with the connection tabs, and a protective circuit module (21) in which grooves (22, 23) with which the connection plates are combined are formed.
Abstract:
A module component in which chip parts are embedded in a circuit board and a method of manufacturing of the same. The module component can have desired circuit characteristics and functions stably even if the size of a part is miniaturized, is produced with high efficiency, and suitable for mechanical mounting. Since a desired circuit is formed by arranging a prescribed number of parts according to a prescribed rule, no heat treatment of embedded parts is required when making a module. Since each chip part has values conforming to the specifications, the circuit characteristic, functions and dimensional accuracy or the like can be stably obtained as designed. Since the chip parts are arranged according to the prescribed rule, insertion of the chip parts can be easily automated and speeded up, and miniaturization of the chip parts is coped with sufficiently. Moreover, the circuit structure can be changed flexibly and easily only by changing the insertion positions and types of chip parts.
Abstract:
An electrical assembly including a substantially planar substrate having at least one recess therein and a plurality of electrical components. The electrical components are positioned in the at least one recess and include a first electrical component and a second electrical component. Each of the electrical components has a body and an electrical connection. The electrical connection of the first electrical component and the electrical connection of the second electrical component are aligned with each other when the body of the first electrical component is in a recess and the body of the second electrical component is in a recess.
Abstract:
The aim of the disclosed invention is to provide a capacitor-built-in-type printed wiring substrate which can reliably eliminate noise and attains extremely low resistance and low inductance involved in connection between an IC chip and the capacitor and to provide a printed wiring substrate and a capacitor used in the same. To achieve this object, a capacitor-built-in-type printed wiring substrate (100) on which an IC chip is mounted includes a capacitor-built-in-type printed wiring substrate (110) and an IC chip (101) mounted on the capacitor-built-in-type printed wiring substrate (110). A printed wiring substrate (120) includes a number of connection-to-IC substrate bumps (152) and a closed-bottomed capacitor accommodation cavity (121) formed therein. A capacitor (130) is disposed in the cavity (121) and includes a pair of electrode groups (133E and 133F) and a number of connection-to-IC capacitor bumps (131) connected to either one of the paired electrode groups (133E and 133F). The connection-to-IC capacitor bumps (131) are flip-chip-bonded to corresponding connection-to-capacitor bumps (103) on the IC chip. The connection-to-IC substrate bumps (152) are flip-chip-bonded to corresponding connection-to-substrate bumps (104) on the IC chip.
Abstract:
In the past, a power supply distance between a power source and an LSI package could not be shortened and power supply variations could easily produce an adverse effect. In the present invention, a power supply module 11 is mounted on the surface of an LSI package 13 . The power supply distance between the LSI 19 and power supply module 11 can be shortened. As a result, the power source noise can be reduced, the efficiency and response rate of the power source unit are high, and the generated electromagnetic field can be reduced. Moreover, since each LSI package has a power supply module required therefor, the number of required power source types (voltage types) on the substrate with the package mounted thereon can be decreased. As a result, the mounting efficiency can be increased and the substrate can be manufactured at a low cost.
Abstract:
A multilayer capacitor having a low parasitic inductance includes a plurality of first electrode and a second electrode plates (e.g. 412-418), a dielectric (402-410) , a first contact (420), and a second contact (422). The first electrode (e.g. 412) is substantially rectangular and it includes a first contact finger (430). The dielectric has a first surface and a second surface, wherein the first and second surfaces are situated opposite with each other. The first surface of the dielectric is coupled with the first electrode. The second electrode (e.g. 442) is substantially rectangular and it includes a first contact finger (432). The second electrode is coupled to the second surface of the dielectric. The first contact (420) is coupled to the first contact finger (430) of the first electrode (e.g. 412). The second contact (422) is coupled to the first contact finger (432) of the second electrode (e.g. 442). The second contact is situated at a minimal space (e.g. 442) from the first contact to reduce the parasitic inductance.