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    HIGH-SPEED PROGRAMMABLE CLOCK DIVIDER
    13.
    发明公开
    HIGH-SPEED PROGRAMMABLE CLOCK DIVIDER 有权

    公开(公告)号：EP3350928A1

    公开(公告)日：2018-07-25

    申请号：EP16754368.5

    申请日：2016-08-10

    申请人： Qualcomm Incorporated

    发明人： AGRAWAL, Neha ,  MOHAMAD, Sajin ,  LEE, Chulkyu

    IPC分类号： H03K21/10 ,  H03K23/64

    CPC分类号： H03K7/06 ,  G06F1/08 ,  H03K3/037 ,  H03K19/21 ,  H03K21/00 ,  H03K21/026 ,  H03K21/10 ,  H03K23/00 ,  H03K23/64

    摘要： Systems and methods for dividing input clock signals by programmable divide ratios can produce output clock signals with the delay from the input clock signal to the output clock signal independent of the value of the divide ratio and with the duty cycle of the output clock signal being 50% independent of the value of the divide ratio. An example programmable clock divider includes a modulo N counter that produces a count signal that counts modulo the divide ratio and a half-rate clock signal generator that produces a common half-rate clock signal, an even half-rate clock signal, and an odd half-rate clock signal that toggle at one-half the rate of the output clock signal. The common half-rate clock signal, the even half-rate clock signal, and the odd half-rate clock signal are combined to produce the output clock signal.

    VOLTAGE MODE DRIVER CIRCUIT FOR N-PHASE SYSTEMS
    14.
    发明授权
    VOLTAGE MODE DRIVER CIRCUIT FOR N-PHASE SYSTEMS 有权
    SPANNUNGSMODUSTREIBERSCHALTUNGFÜRN-PHASIGES系统

    公开(公告)号：EP2965216B1

    公开(公告)日：2017-04-19

    申请号：EP14713350.8

    申请日：2014-03-07

    申请人： Qualcomm Incorporated

    发明人： LEE, Chulkyu ,  WILEY, George Alan ,  SENGOKU, Shoichiro

    IPC分类号： H04B3/06

    CPC分类号： H04B3/06 ,  G06F13/4072 ,  Y02D10/14 ,  Y02D10/151

    摘要： System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within electronic equipment. Transmission lines are selectively terminated in an N-phase polarity encoded transmitter when the transmission lines would otherwise be undriven. Data is mapped to a sequence of symbols to be transmitted on a plurality of wires. The sequence of symbols is encoded in three signals. Each of the three terminals may be driven such that transistors are activated to couple a terminal to first and second voltage levels through a pair of impedances when the terminal would otherwise be undriven. The terminal is then pulled toward an intermediate voltage level while the terminal presents a desired impedance level to a transmission line.

    摘要翻译： 描述了促进数据传输的系统，方法和装置，特别是在电子设备内的两个设备之间。 当传输线否则将被驱动时，传输线选择性地终止在N相极性编码的发射机中。 数据被映射到要在多根线上传输的符号序列。 符号序列被编码为三个信号。 可以驱动三个端子中的每一个，使得晶体管被激活以在端子否则将被驱动时通过一对阻抗将端子耦合到第一和第二电压电平。 然后将终端拉向中间电压电平，同时终端向传输线呈现期望的阻抗电平。

    N-FACTORIAL DIFFERENTIAL SIGNALING TERMINATION NETWORK
    15.
    发明授权
    N-FACTORIAL DIFFERENTIAL SIGNALING TERMINATION NETWORK 有权
    的N- FACTOR差分信令金融网络

    公开(公告)号：EP2965480B1

    公开(公告)日：2017-02-08

    申请号：EP14713723.6

    申请日：2014-03-07

    申请人： Qualcomm Incorporated

    发明人： SENGOKU, Shoichiro ,  WILEY, George Alan ,  LEE, Chulkyu ,  CHEUNG, Joseph

    IPC分类号： H04L25/02

    CPC分类号： H03H2/005 ,  H04B1/04 ,  H04L25/0272 ,  H04L25/0278 ,  H04L25/14 ,  Y02D30/30

    摘要： A termination network circuit for a differential signal transmitter comprises a plurality of n resistance elements and a plurality of differential signal drivers. A first end of each of the resistance elements is coupled at a common node, where n is an integer value and is the number of conductors used to transmit a plurality of differential signals. Each differential signal driver may include a positive terminal driver and a negative terminal driver. The positive terminal driver is coupled to a second end of a first resistance element while the negative terminal driver is coupled to a second end of a second resistance element. The positive terminal driver and the negative terminal driver are separately and independently switchable to provide a current having a magnitude and direction. During a transmission cycle each of the resistance elements has a current of a different magnitude and/or direction than the other resistance elements.

    N-PHASE SIGNAL TRANSITION ALIGNMENT
    16.
    发明公开
    N-PHASE SIGNAL TRANSITION ALIGNMENT 有权
    的N- PHASEN-SIGNALÜBERGANGSAUSRICHTUNG

    公开(公告)号：EP3030972A1

    公开(公告)日：2016-06-15

    申请号：EP14761721.1

    申请日：2014-08-07

    申请人： Qualcomm Incorporated

    发明人： LEE, Chulkyu ,  WILEY, George Alan

    IPC分类号： G06F13/42 ,  H04L25/49

    CPC分类号： G06F13/36 ,  G06F13/4063 ,  G06F13/4068 ,  G06F13/4278 ,  G06F13/4282 ,  H04L7/0033 ,  H04L25/14 ,  H04L25/4917 ,  H04L25/4919 ,  Y02D10/14 ,  Y02D10/151

    摘要： System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Information is transmitted in N-phase polarity encoded symbols. Drivers may be adapted or configured to align state transitions on two or more connectors in order to minimize a transition period between consecutive symbols. The drivers may include circuits that advance or delay certain transitions. The drivers may include pre-emphasis circuits that operate to drive the state of a connector for a portion of the transition period, even when the connector is transitioned to an undriven state.

    摘要翻译： 描述了促进数据传输的系统，方法和装置，特别是在电子设备内的两个设备之间。 信息以N相极性编码符号发送。 驱动器可以被调整或配置成在两个或更多个连接器上对准状态转换，以便使连续符号之间的转换周期最小化。 驱动器可以包括推进或延迟某些转换的电路。 驱动器可以包括预加重电路，其操作以在过渡期的一部分中驱动连接器的状态，即使当连接器转换到未驱动状态时。